參數(shù)資料
型號： APMOTOR56F8000E
廠商： Freescale Semiconductor
文件頁數(shù)： 78/124頁
文件大?。?/td> 0K
描述： KIT DEMO MOTOR CTRL SYSTEM
標(biāo)準(zhǔn)包裝： 1
附件類型： 電機控制器
適用于相關(guān)產(chǎn)品： DEMO56F8013，DEMO56F8013-E
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MC56F8006VLC-ND - DSC 16K FLASH 32MHZ 32-LQFP
MC56F8002VWL-ND - DSC 12K FLASH 32MHZ 28-SOIC
DEMO56F8014-E-ND - BOARD DEMO MC56F8014 W/UNIV PS
DEMO56F8014-ND - BOARD DEMO MC56F8014 W/US PS
DEMO56F8014-EE-ND - BOARD DEMO FOR 56F8014
DEMO56F8013-EE-ND - BOARD DEMO FOR 56F8013
MC56F8014VFAE-ND - IC DIGITAL SIGNAL CTRLR 32-LQFP
MC56F8013VFAE-ND - IC DIGITAL SIGNAL CTLR 32-LQFP
更多...
Register Descriptions
56F8014 Technical Data, Rev. 11
Freescale Semiconductor
57
5.5.8
Fast Interrupt 0 Vector Address Low Register (FIVAL0)
Figure 5-10 Fast Interrupt 0 Vector Address Low Register (FIVAL0)
5.5.8.1
Fast Interrupt 0 Vector Address Low (FIVAL0)—Bits 15—0
The lower 16 bits of the vector address used for Fast Interrupt 0. This register is combined with FIVAH0
to form the 21-bit vector address for Fast Interrupt 0 defined in the FIM0 register.
5.5.9
Fast Interrupt 0 Vector Address High Register (FIVAH0)
Figure 5-11 Fast Interrupt 0 Vector Address High Register (FIVAH0)
5.5.9.1
Reserved—Bits 15–5
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
5.5.9.2
Fast Interrupt 0 Vector Address High (FIVAH0)—Bits 4–0
The upper five bits of the vector address used for Fast Interrupt 0. This register is combined with FIVAL0
to form the 21-bit vector address for Fast Interrupt 0 defined in the FIM0 register.
5.5.10
Fast Interrupt 1 Match Register (FIM1)
Figure 5-12 Fast Interrupt 1 Match Register (FIM1)
5.5.10.1
Reserved—Bits 15–6
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
5.5.10.2
Fast Interrupt 1 Vector Number (FAST INTERRUPT 1)—Bits 5–0
These values determine which IRQ will be Fast Interrupt 1. Fast Interrupts vector directly to a service
routine based on values in the Fast Interrupt Vector Address registers without having to go to a jump table
first. IRQs used as Fast Interrupts must be set to priority level 2. Unexpected results will occur if a Fast
Base + $7
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Read
FAST INTERRUPT 0 VECTOR ADDRESS LOW
Write
RESET
00000
0000000
0000
Base + $8
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Read
0
FAST INTERRUPT 0 VECTOR
ADDRESS HIGH
Write
RESET
00000
0000000
0000
Base + $9
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Read
0
FAST INTERRUPT 1
Write
RESET
00000
0000000
0000
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