參數(shù)資料
型號： APMOTOR56F8000E
廠商： Freescale Semiconductor
文件頁數(shù)： 47/124頁
文件大?。?/td> 0K
描述： KIT DEMO MOTOR CTRL SYSTEM
標準包裝： 1
附件類型： 電機控制器
適用于相關產(chǎn)品： DEMO56F8013，DEMO56F8013-E
相關產(chǎn)品： MC56F8006VWL-ND - DSC 16K FLASH 32MHZ 28-SOIC
MC56F8006VLF-ND - DSC 16K FLASH 32MHZ 48-LQFP
MC56F8006VLC-ND - DSC 16K FLASH 32MHZ 32-LQFP
MC56F8002VWL-ND - DSC 12K FLASH 32MHZ 28-SOIC
DEMO56F8014-E-ND - BOARD DEMO MC56F8014 W/UNIV PS
DEMO56F8014-ND - BOARD DEMO MC56F8014 W/US PS
DEMO56F8014-EE-ND - BOARD DEMO FOR 56F8014
DEMO56F8013-EE-ND - BOARD DEMO FOR 56F8013
MC56F8014VFAE-ND - IC DIGITAL SIGNAL CTRLR 32-LQFP
MC56F8013VFAE-ND - IC DIGITAL SIGNAL CTLR 32-LQFP
更多...
Pin Descriptions
56F8014 Technical Data, Rev. 11
Freescale Semiconductor
29
3.5 Pin Descriptions
3.5.1
External Reference (GPIOB6 / RXD / SDA / CLKIN)
After reset, the internal relaxation oscillator is selected as the clock source for the chip. The user then has
the option of switching to an external clock reference by enabling the PRECS bit in the OCCS Oscillator
Control register, if desired.
Part 4 Memory Map
4.1 Introduction
The 56F8014 device is a 16-bit motor-control chip based on the 56800E core. It uses a Harvard-style
architecture with two independent memory spaces for Data and Program. On-chip RAM is used in both
spaces and Flash memory is used only in Program space.
This section provides memory maps for:
Program Address Space, including the Interrupt Vector Table
Data Address Space, including the EOnCE Memory and Peripheral Memory Maps
On-chip memory sizes for the device are summarized in Table 4-1. Flash memories’ restrictions are
identified in the “Use Restrictions” column of Table 4-1.
4.2 Interrupt Vector Table
Table 4-2 provides the 56F8014’s reset and interrupt priority structure, including on-chip peripherals. The
table is organized with higher-priority vectors at the top and lower-priority interrupts lower in the table.
As indicated, the priority of an interrupt can be assigned to different levels, allowing some control over
interrupt priorities. All level 3 interrupts will be serviced before level 2, and so on. For a selected priority
level, the lowest vector number has the highest priority.
The location of the vector table is determined by the Vector Base Address (VBA). Please see Section 5.5.6
for the reset value of the VBA.
By default, the chip reset address and COP reset address will correspond to vector 0 and 1 of the interrupt
vector table. In these instances, the first two locations in the vector table must contain branch or JMP
instructions. All other entries must contain JSR instructions.
Table 4-1 Chip Memory Configurations
On-Chip Memory
56F8014
Use Restrictions
Program Flash
(PFLASH)
8k x 16
Erase / Program via Flash interface unit and word writes to CDBW
Unified RAM (ram)
2k x 16
Usable by both the Program and Data memory spaces
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