參數(shù)資料
型號： APMOTOR56F8000E
廠商： Freescale Semiconductor
文件頁數(shù)： 52/124頁
文件大?。?/td> 0K
描述： KIT DEMO MOTOR CTRL SYSTEM
標準包裝： 1
附件類型： 電機控制器
適用于相關產(chǎn)品： DEMO56F8013，DEMO56F8013-E
相關產(chǎn)品： MC56F8006VWL-ND - DSC 16K FLASH 32MHZ 28-SOIC
MC56F8006VLF-ND - DSC 16K FLASH 32MHZ 48-LQFP
MC56F8006VLC-ND - DSC 16K FLASH 32MHZ 32-LQFP
MC56F8002VWL-ND - DSC 12K FLASH 32MHZ 28-SOIC
DEMO56F8014-E-ND - BOARD DEMO MC56F8014 W/UNIV PS
DEMO56F8014-ND - BOARD DEMO MC56F8014 W/US PS
DEMO56F8014-EE-ND - BOARD DEMO FOR 56F8014
DEMO56F8013-EE-ND - BOARD DEMO FOR 56F8013
MC56F8014VFAE-ND - IC DIGITAL SIGNAL CTRLR 32-LQFP
MC56F8013VFAE-ND - IC DIGITAL SIGNAL CTLR 32-LQFP
更多...
Peripheral Memory Mapped Registers
56F8014 Technical Data, Rev. 11
Freescale Semiconductor
33
4.6 Peripheral Memory Mapped Registers
On-chip peripheral registers are part of the data memory map on the 56800E series. These locations may
be accessed with the same addressing modes used for ordinary Data memory, except all peripheral
registers should be read/written using word accesses only.
Table 4-6 summarizes base addresses for the set of peripherals on the 56F8014 device. Peripherals are
listed in order of the base address.
Table 4-5 EOnCE Memory Map
Address
Register Acronym
Register Name
X:$FF FFFF
OTX1 / ORX1
Transmit Register Upper Word
Receive Register Upper Word
X:$FF FFFE
OTX / ORX (32 bits)
Transmit Register
Receive Register
X:$FF FFFD
OTXRXSR
Transmit and Receive Status and Control Register
X:$FF FFFC
OCLSR
Core Lock / Unlock Status Register
X:$FF FFFB - X:$FF FFA1
Reserved
X:$FF FFA0
OCR
Control Register
X:$FF FF9F
Instruction Step Counter
X:$FF FF9E
OSCNTR (24 bits)
Instruction Step Counter
X:$FF FF9D
OSR
Status Register
X:$FF FF9C
OBASE
Peripheral Base Address Register
X:$FF FF9B
OTBCR
Trace Buffer Control Register
X:$FF FF9A
OTBPR
Trace Buffer Pointer Register
X:$FF FF99
Trace Buffer Register Stages
X:$FF FF98
OTB (21 - 24 bits/stage)
Trace Buffer Register Stages
X:$FF FF97
Breakpoint Unit Control Register
X:$FF FF96
OBCR (24 bits)
Breakpoint Unit Control Register
X:$FF FF95
Breakpoint Unit Address Register 1
X:$FF FF94
OBAR1 (24 bits)
Breakpoint Unit Address Register 1
X:$FF FF93
Breakpoint Unit Address Register 2
X:$FF FF92
OBAR2 (32 bits)
Breakpoint Unit Address Register 2
X:$FF FF91
Breakpoint Unit Mask Register 2
X:$FF FF90
OBMSK (32 bits)
Breakpoint Unit Mask Register 2
X:$FF FF8F
Reserved
X:$FF FF8E
OBCNTR
EOnCE Breakpoint Unit Counter
X:$FF FF8D
Reserved
X:$FF FF8C
Reserved
X:$FF FF8B
Reserved
X:$FF FF8A
OESCR
External Signal Control Register
X:$FF FF89 - X:$FF FF00
Reserved
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