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| 型號(hào)： | CR16HCT5VJE9Y |
| 英文描述： | Microcontroller |
| 中文描述： | 微控制器 |
| 文件頁(yè)數(shù)： | 51/157頁(yè) |
| 文件大小： | 1256K |
| 代理商： | CR16HCT5VJE9Y |
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15.2
Each timer/counter unit can be configured to operate in any
of the following modes:
— Processor-Independent Pulse
(PWM) mode
— Dual Input Capture mode
— Dual Independent Timer mode
— Single Input Capture and Single Timer mode
Upon reset, the timers are disabled. To configure and start
the timers, the software must write a set of values to the reg-
isters that control the timers. The registers are described in
Section 15.5.
TIMER OPERATING MODES
Width
Modulation
15.2.1
Mode 1 is the Processor-Independent Pulse Width Modula-
tion (PWM) mode, which generates pulses of a specified
width and duty cycle, and which also provides a separate
general-purpose timer/counter.
Figure 14 is a block diagram of the Multi-Function Timer con-
figured to operate in Mode 1. Timer/Counter I (TnCNT1)
functions as the time base for the PWM timer. It counts down
at the clock rate selected for the counter. When an underflow
occurs, the timer register is reloaded alternately from the
TnCRA and TnCRB register, and counting proceeds down-
ward from the loaded value.
Mode 1: Processor-Independent PWM
On the first underflow, the timer is loaded from TnCRA, then
from TnCRB on the next underflow, then from TnCRA again
on the next underflow, and so on. Every time the counter is
stopped and restarted, it always obtains its first reload value
from TnCRA. This is true whether the timer is restarted upon
reset, after entering Mode 1 from another mode, or after
stopping and restarting the clock with the Timer/Counter I
clock selector.
The timer can be configured to toggle the TnA output bit upon
each underflow. This generates a clock signal on TnA with
the width and duty cycle determined by the values stored in
the TnCRA and TnCRB registers. This is a “processor-inde-
pendent” PWM clock because once the timer is set up, no
more action is required from the CPU to generate a continu-
ous PWM signal.
The timer can be configured to generate separate interrupts
upon reload from TnCRA and TnCRB. The interrupts can be
enabled or disabled under software control. The CPU can
determine the cause of each interrupt by looking at the
TnAPND and TnBPND flags, which are set by the hardware
upon each occurrence of a timer reload.
In Mode 1, Timer/Counter II (TnCNT2) can be used either as
a simple system timer, an external event counter, or a pulse
accumulate counter. The clock counts down using the clock
selected with the Timer/Counter II clock selector. It generates
an interrupt upon each underflow if the interrupt is enabled
with the TnDIEN bit.
15.2.2
Mode 2 is the Dual Input Capture mode, which measures the
elapsed time between occurrences of external events, and
which also provides a separate general-purpose timer/
counter.
Figure 15 is a block diagram of the Multi-Function Timer con-
figured to operate in Mode 2. The time base of the capture
timer depends on Timer/Counter I, which counts down using
the clock selected with the Timer/Counter I clock selector.
Mode 2: Dual Input Capture
Figure 14.
Mode 1: Processor-Independent PWM Block Diagram
Reload A = Time 1
TnCRA
Timer/Counter I
TnCNT1
Reload B = Time 2
TnCRB
Timer I
Clock
Underflow
TnA
TnAIEN
TnAPND
TnBIEN
TnBPND
Timer
Interrupt A
Timer
Interrupt B
TnAEN
Timer/Counter II
TnCNT2
Timer II
Clock
TnDIEN
TnDPND
Timer
Interrupt D
TnB
Clock
Selector
Underflow
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| CR16HCT9VJE7Y | Microcontroller |
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相關(guān)代理商/技術(shù)參數(shù) |
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| CR16HCT5VJEXY | 制造商:NSC 制造商全稱(chēng):National Semiconductor 功能描述:CR16MCT9/CR16MCT5/CR16HCT9/CR16HCT5 16-Bit Reprogrammable/ROM Microcontroller |
| CR16HCT9 | 制造商:NSC 制造商全稱(chēng):National Semiconductor 功能描述:CR16MCT9/CR16MCT5/CR16HCT9/CR16HCT5 16-Bit Reprogrammable/ROM Microcontroller |
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| CR16HCT9VJE7Y | 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:Microcontroller |
| CR16HCT9VJE8 | 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:Microcontroller |
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