參數(shù)資料
型號(hào): CR16HCT5VJE9Y
英文描述: Microcontroller
中文描述: 微控制器
文件頁數(shù): 94/157頁
文件大小: 1256K
代理商: CR16HCT5VJE9Y
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94
Re-synchronization is performed according to the following
rules:
If the magnitude of e is less or equal to the programmed
value of SJW, re-synchronization will have the same effect
as hard synchronization.
If e > SJW, the time segment 1 will be lengthened by the
value of the SJW (see Figure 53).
If e < -SJW, the time segment 2 will be shortened by the
value SJW (see Figure 54).
20.2.4
The CAN prescaler (PSC) is shown is Figure 55. It divides
the CKI input clock by the value defined in the CTIM register.
The resulting clock is called time quanta clock and defines
the length of one time quanta (tq).
Please refer to CAN Timing Register (CTIM) on page 111 for
a detailed description of the CTIM register.
Note:
PSC is the value of the clock prescaler. TSEG1 and
TSEG2 are the length of time segment 1 and 2 in tq.
The resulting bus clock can be calculated by the equation:
Clock Generator
The values of PSC and TSEG 1 and 2 are specified by the
contents of the registers PSC, TSEG1 and TSEG2 as fol-
lows:
PSC = PSC[5:0] + 2
TSEG1 = TSEG1[3:0] + 1
TSEG2 = TSEG2 [2 : 0] + 1
BUS SIGNAL
CAN
CLOCK
PREVIOUS
BIT
A
TSEG1
TSEG2
NEXT BIT
PREVIOUS
BIT
A
TSEG1
TSEG2
NEXT BIT
SJW
“NORMAL” BIT TIME
BIT TIME LENGTHENED BY SJW
e
Figure 53.
Re-synchronization (e > SJW)
BUS SIGNAL
CAN
CLOCK
PREVIOUS
BIT
A
TSEG1
TSEG2
“NOMINAL” BIT TIME
PRBIT
TSEG1
TSEG2
NEXT BIT
BIT TIME SHORTENED BY SJW
Figure 54.
Re-synchronization (e < -SJW)
e
busclock
TSEG
1
PSC
(
)
x
1
(
TSEG
2
+
+
)
-------------------------------------CKI
=
Figure 55.
Bit Rate Generation
PSC
:
internal time
quanta clock (1/tq)
bit rate
CKI
(1+TSEG1+TSEG2)
:
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