- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄366891 > CR16HCT5VJE9Y Microcontroller PDF資料下載
參數(shù)資料
| 型號(hào)： | CR16HCT5VJE9Y |
| 英文描述： | Microcontroller |
| 中文描述： | 微控制器 |
| 文件頁(yè)數(shù)： | 80/157頁(yè) |
| 文件大?。?/td> | 1256K |
| 代理商： | CR16HCT5VJE9Y |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)當(dāng)前第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)
www.national.com
80
19.2.1
An ACCESS.bus transaction starts with a master device re-
questing bus mastership. It sends a Start Condition, followed
by the address of the device it wants to access. If this trans-
action is successfully completed, the software can assume
that the device has become the bus master.
For a device to become the bus master, the software should
perform the following steps:
1. Set ACBCTL1.START, and configure ACBCTL1.INTEN
to the desired operation mode (Polling or Interrupt). This
causes the ACB to issue a Start Condition on the AC-
CESS.bus, as soon as the ACCESS.bus is free
(ACBCST.BB=0). It then stalls the bus by holding SCL
low.
2. If a bus conflict is detected, (i.e., some other device pulls
down the SCL signal before this device does), ACB-
ST.BER is set.
3. If there is no bus conflict, ACBST.MASTER and ACB-
ST.SDAST are set.
4. If ACBCTL1.INTEN is set, and either ACBST.BER or
ACBST.SDAST is set, an interrupt is sent to the ICU.
Master Mode
Sending the Address Byte
Once this device is the active master of the ACCESS.bus
(ACBST.MASTER is set), it can send the address on the bus.
The address sent should not be this device’s own address as
defined in ACBADDR.ADDR if ACBADDR.SAEN is set, nor
should it be the global call address if ACBST.GCMTCH is set.
To send the address byte use the following sequence:
1. Configure the ACBCTL1.INTEN bit according to the de-
sired operation mode. For a receive transaction where
the software wants only one byte of data, it should set
the ACBCTL1.ACK bit.
If only an address needs to be sent, set (1) the
ACBCTL1.STASTRE bit.
2. Write the address byte (7-bit target device address), and
the direction bit, to the ACBSDA register. This causes
the module to generate a transaction. At the end of this
transaction, the acknowledge bit received is copied to
ACBST.NEGACK. During the transaction the SDA and
SCL lines are continuously checked for conflict with oth-
er devices. If a conflict is detected, the transaction is
aborted, ACBST.BER is set, and ACBST.MASTER is
cleared.
3. If ACBCTL1.STASTRE is set, and the transaction was
successfully completed (i.e., both ACBST.BER and
ACBST.NEGACK are cleared), ACBST.STASTR is set.
In this case, the ACB stalls any further ACCESS.bus op-
erations (i.e., holds SCL low). If ACBCTL1.INTE is set, it
also sends an interrupt to the core.
4. If the requested direction is transmit, and the start trans-
action was completed successfully (i.e., neither ACB-
ST.NEGACK nor ACBST.BER is set, and no other
master has accessed the device), ACBST.SDAST is set
to indicate that the module awaits attention.
5. If the requested direction is receive, the start transaction
was completed successfully and ACBCTL1.STASTRE is
cleared, the module starts receiving the first byte auto-
matically.
6. Check that both ACBST.BER and ACBST.NEGACK are
cleared. If the ACBCTL1.INTEN bit is set, an interrupt is
generated
when
either
ST.NEGACK is set.
ACBST.BER
or
ACB-
Master Transmit
After becoming the bus master, the device can start transmit-
ting data on the ACCESS.bus.
To transmit a byte, the software should:
1. Check that the BER and NEGACK bits in ACBST are
cleared
and
ACBST.SDAST
ACBCTL1.STASTRE is set, check that ACBST.STASTR
is cleared.
2. Write the data byte to be transmitted to the ACBSDA
register.
When the slave responds with a negative acknowledge, the
ACBST.NEGACK bit is set and the ACBST.SDAST bit re-
mains cleared. In this case, if ACBCTL1.INTEN is set, an in-
terrupt is sent to the core.
is
set.
Also,
if
Master Receive
After becoming the bus master, the device can start receiving
data on the ACCESS.bus.
To receive a byte, the software should:
1. Check that ACBST.SDAST is set and ACBST.BER is
cleared. Also, if ACBCTL1.STASTRE is set, check that
ACBST.STASTR is cleared.
2. Set the ACBCTL1.ACK bit to 1, if the next byte is the last
byte that should be read. This causes a negative ac-
knowledge to be sent.
3. Read the data byte from the ACBSDA register.
Master Stop
A Stop Condition may be issued only when this device is the
active bus master (ACBST.MASTRER=1). To end a transac-
tion, set (1) ACBCTL1.STOP before clearing the current stall
flag (i.e., ACBST.SDAST, ACBST.NEGACK or ACB-
ST.STASTR). This causes the module to send a Stop Condi-
tion immediately, and clear ACBCTL1.STOP.
Master Bus Stall
The ACB module can stall the ACCESS.bus between trans-
fers while waiting for the core’s response. The ACCESS.bus
is stalled by holding the SCL signal low after the acknowl-
edge cycle. Note that this is interpreted as the beginning of
the following bus operation. The user must make sure that
the next operation is prepared before the flag that causes the
bus stall is cleared.
The flags that can cause a stall in master mode are:
— Negative acknowledge after sending a byte (ACBST-
NEGACK=1).
— ACBST.SDAST bit is set.
— If ACBCTL1.STASTRE=1, after a successful start
(ACBST.STASTR=1).
Repeated Start
A repeated start is performed when this device is already the
bus master (ACBST.MASTER is set). In this case the AC-
CESS.bus is stalled and the ACB is awaiting the core han-
dling due to: negative acknowledge (ACBST.NEGACK=1),
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CR16HCT9 | |
| CR16HCT9VJE7 | Microcontroller |
| CR16HCT9VJE7Y | Microcontroller |
| CR16HCT9VJE8 | Microcontroller |
| CR16HCT9VJE8Y | Microcontroller |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CR16HCT5VJEXY | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:CR16MCT9/CR16MCT5/CR16HCT9/CR16HCT5 16-Bit Reprogrammable/ROM Microcontroller |
| CR16HCT9 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:CR16MCT9/CR16MCT5/CR16HCT9/CR16HCT5 16-Bit Reprogrammable/ROM Microcontroller |
| CR16HCT9VJE7 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microcontroller |
| CR16HCT9VJE7Y | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microcontroller |
| CR16HCT9VJE8 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microcontroller |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。