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| 型號： | CR16HCT5VJE9Y |
| 英文描述： | Microcontroller |
| 中文描述： | 微控制器 |
| 文件頁數(shù)： | 68/157頁 |
| 文件大?。?/td> | 1256K |
| 代理商： | CR16HCT5VJE9Y |
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MSK goes idle again. The MSK idle state can be either high
or low, depending on the MIDL bit.
17.3
In Slave mode, the MSK pin is an input for the shift clock
MSK. MDIDO is placed in TRI-STATE mode when MCS is in-
active. Data transfer is enabled when MCS is active.
The slave starts driving MDIDO when MCS is activated. The
most significant bit (lower byte in 8-bit mode or upper byte in
16-bit mode) is output onto the MDIDO pin first. After eight or
sixteen clocks (depending on the selected mode), the data
transfer is completed.
If a new shift process starts before MWDAT was written, i.e.,
while MWDAT does not contain any valid data, and the “Echo
Enable” (MECH) bit is set to 1, the data received from MDODI
is transmitted on MDIDO in addition to being shifted to MW-
DAT. If the MECH bit is cleared to 0, the data transmitted on
MDIDO is the data held in the MWDAT register, regardless of
its validity. The master may negate the MCS signal to syn-
chronize the bit count between the master and the slave. In
the case that the slave is the only slave in the system, MCS
can be tied to V
SS
.
17.4
INTERRUPT GENERATION
An interrupt is generated in any of the following cases:
— When the read buffer is full (MRBF=1) and the “Enable
Interrupt for Read” bit is set (MEIR=1).
— Whenever the shifter is not busy, i.e. the MBSY bit is
cleared (MBSY=0) and the “Enable Interrupt for Write”
bit is set (MEIW=1).
— When an overrun condition occurs (MOVR is set to 1)
and the “Enable Interrupt on Overrun” bit is set
(MEIO=1). This usage is restricted to master mode.
Figure 30 illustrates the various interrupt capabilities of this
module.
SLAVE MODE
17.5
The software interacts with the MICROWIRE interface by ac-
cessing the MICROWIRE registers. There are five such reg-
isters:
— MICROWIRE Data Register (MWDAT)
MICROWIRE INTERFACE REGISTERS
— MICROWIRE Control Register (MWCTL)
— MICROWIRE Status Register (MWSTAT)
17.5.1
The MWDAT register is a word-wide, read/write register used
to transmit and receive data through the MDODI and MDIDO
pins. Figure 31 shows the hardware structure of the register.
MICROWIRE Data Register (MWDAT)
Figure 29.
Alternate Mode, MIDL Bit = 1
End of Transfer
Sample Point
Shift Out
Data Out
Data In
msb
msb-1
msb-2
Bit 1
Bit 0 (lsb)
msb
msb-1
msb-2
Bit 1
Bit 0 (lsb)
MSKn
Figure 30.
MWSPI Interrupts
Interrupt
MWSPI
MOVR = 1
MRBF = 1
MBSY = 0
MEIW
MEIR
MEIO
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| CR16HCT9 | |
| CR16HCT9VJE7 | Microcontroller |
| CR16HCT9VJE7Y | Microcontroller |
| CR16HCT9VJE8 | Microcontroller |
| CR16HCT9VJE8Y | Microcontroller |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| CR16HCT5VJEXY | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:CR16MCT9/CR16MCT5/CR16HCT9/CR16HCT5 16-Bit Reprogrammable/ROM Microcontroller |
| CR16HCT9 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:CR16MCT9/CR16MCT5/CR16HCT9/CR16HCT5 16-Bit Reprogrammable/ROM Microcontroller |
| CR16HCT9VJE7 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microcontroller |
| CR16HCT9VJE7Y | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microcontroller |
| CR16HCT9VJE8 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microcontroller |
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