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| 型號： | CR16HCT5VJE9Y |
| 英文描述： | Microcontroller |
| 中文描述： | 微控制器 |
| 文件頁數(shù)： | 92/157頁 |
| 文件大小： | 1256K |
| 代理商： | CR16HCT5VJE9Y |
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92
Error Counters
The CR16CAN module contains two error counters to per-
form the error management. The receive error counter (REC)
and the transmit error counter (TEC) are 8-bits wide, located
in the 16-bit wide CANEC register. The counters are modified
by the CR16CAN according to the rules listed in Table 20 “Er-
ror Counter Handling”.
The Error counters can be read by the users software as de-
scribed under CAN Error Counter Register (CANEC) on page
114.
ERROR
ACTIVE
(TEC AND REC) < 128
BUS
OFF
TEC > 255
128 occurrences of
11 consecutive ‘recessive’ bits
Figure 51.
CR16CAN Bus States
PASSIVE
(TEC OR REC) > 127
ERROR
ERROR
WARNING
(TEC OR REC) > 95
(TEC AND REC) < 96
SYNC
11 consecutive ‘recessive’ bits
received
external RESET or
enable CR16CAN
Table 20
Error Counter Handling
Condition
a
Action
Receive Error Counter Conditions
b
A receiver detects a Bit Error during sending an active error flag.
increment by 8
A receiver detects a ‘dominant’ bit as the first bit after sending an error flag
increment by 8
After detecting the 14th consecutive ‘dominant’ bit following an active error flag or overload
flag, or after detecting the 8th consecutive ‘dominant’ bit following a passive error flag.
After each sequence of additional 8 consecutive ‘dominant’ bits.
increment by 8
Any other error condition (stuff, frame, CRC, ACK)
increment by 1
A valid reception or transmission
decrement by 1 unless
counter is already 0
Transmit Error Counter Conditions
A transmitter detects a Bit Error during sending an active error flag
increment by 8
After detecting the 14th consecutive ‘dominant’ bit following an active error flag or overload flag
or after detecting the 8th consecutive ‘dominant’ bit following a passive error flag.
After each sequence of additional 8 consecutive ‘dominant’ bits.
increment by 8
Any other error condition (stuff, frame, CRC, ACK)
increment by 8
A valid reception or transmission
decrement by 1 unless
counter is already 0
a. This table provides an overview of the CAN error conditions and the behavior of the CR16CAN; for a detailed description of the
error management and fault confinement rules, please refer to the CAN Specification 2.0B
b. If the MSB (bit 7) of the REC is set, the node is error passive and the REC will not increment any further.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| CR16HCT5VJEXY | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:CR16MCT9/CR16MCT5/CR16HCT9/CR16HCT5 16-Bit Reprogrammable/ROM Microcontroller |
| CR16HCT9 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:CR16MCT9/CR16MCT5/CR16HCT9/CR16HCT5 16-Bit Reprogrammable/ROM Microcontroller |
| CR16HCT9VJE7 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microcontroller |
| CR16HCT9VJE7Y | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microcontroller |
| CR16HCT9VJE8 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microcontroller |
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