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參數資料
| 型號： | CY7C1339G-200AXCT |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | SRAM |
| 英文描述： | 128K X 32 CACHE SRAM, 2.8 ns, PQFP100 |
| 封裝： | 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, MS-026, TQFP-100 |
| 文件頁數： | 12/18頁 |
| 文件大?。?/td> | 386K |
| 代理商： | CY7C1339G-200AXCT |
CY7C1339G
Document #: 38-05520 Rev. *F
Page 3 of 18
Pin Configurations (continued)
Pin Definitions
Name
I/O
Description
A0, A1, A
Input-
Synchronous
Address Inputs used to select one of the 128K address locations. Sampled at the rising edge
of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 are sampled active. A1, A0
are fed to the two-bit counter..
BWA, BWB
BWC, BWD
Input-
Synchronous
Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes to the SRAM.
Sampled on the rising edge of CLK.
GW
Input-
Synchronous
Global Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK, a global
write is conducted (ALL bytes are written, regardless of the values on BW[A:D] and BWE).
BWE
Input-
Synchronous
Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal must be
asserted LOW to conduct a byte write.
CLK
Input-
Clock
Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the
burst counter when ADV is asserted LOW, during a burst operation.
CE1
Input-
Synchronous
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE2 and CE3 to select/deselect the device. ADSP is ignored if CE1 is HIGH. CE1 is sampled only
when a new external address is loaded.
CE2
Input-
Synchronous
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with
CE1 and CE3 to select/deselect the device.CE2 is sampled only when a new external address is
loaded.
CE3
Input-
Synchronous
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE1 and CE2 to select/deselect the device. CE3 is sampled only when a new external address is
loaded. Not connected for BGA. Where referenced, CE3 is assumed active throughout this
document for BGA.
OE
Input-
Asynchronous
Output Enable, asynchronous input, active LOW. Controls the direction of the I/O pins. When
LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tri-stated, and act as
input data pins. OE is masked during the first clock of a read cycle when emerging from a
deselected state.
23
4
5
6
7
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
VDDQ
NC/288M
NC/144M
NC
DQC
DQD
DQC
DQD
AA
A
ADSP
VDDQ
CE2
A
DQC
VDDQ
DQC
VDDQ
DQD
NC
VDDQ
VDD
CLK
VDD
VSS
NC/576M
NC/1G
NC
NC/36M
NC/72M
NC
VDDQ
AA
A
NC/9M
A
A0
A1
DQA
DQC
DQA
DQB
DQA
DQB
VDD
DQC
VDD
DQD
ADSC
NC
CE1
OE
ADV
GW
VSS
NC
MODE
NC
BWB
BWc
NC
VDD
NC
BWA
NC
BWE
BWD
ZZ
119-Ball BGA Pinout
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相關代理商/技術參數 |
參數描述 |
|---|---|
| CY7C1339G-200BGI | 功能描述:靜態(tài)隨機存取存儲器 128Kx32 3.3V IND Sync FT 靜態(tài)隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1339G-200BGIT | 功能描述:靜態(tài)隨機存取存儲器 128Kx32 3.3V IND Sync FT 靜態(tài)隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1339G-200BGXI | 制造商:Cypress Semiconductor 功能描述:SRAM SYNC QUAD 3.3V 4MBIT 128KX32 2.8NS 119BGA - Bulk |
| CY7C1339L-15ZIT | 制造商:Cypress Semiconductor 功能描述:ELECTRONIC COMPONENT |
| CY7C1339S-133AXC | 功能描述:靜態(tài)隨機存取存儲器 CY7C1339S-133AXC RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
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