參數(shù)資料
型號： CY7C1339G-200AXCT
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： SRAM
英文描述： 128K X 32 CACHE SRAM, 2.8 ns, PQFP100
封裝： 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, MS-026, TQFP-100
文件頁數(shù)： 17/18頁
文件大?。?/td> 386K
代理商： CY7C1339G-200AXCT
CY7C1339G
Document #: 38-05520 Rev. *F
Page 8 of 18
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Supply Voltage on VDD Relative to GND........ –0.5V to +4.6V
Supply Voltage on VDDQ Relative to GND ...... –0.5V to +VDD
DC Voltage Applied to Outputs
in tri-state ............................................ –0.5V to VDDQ + 0.5V
DC Input Voltage ................................... –0.5V to VDD + 0.5V
Current into Outputs (LOW)......................................... 20 mA
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current.................................................... > 200 mA
Operating Range
Range
Ambient
Temperature
VDD
VDDQ
Commercial
0°C to +70°C
3.3V
–5%/+10%
2.5V –5%
to VDD
Industrial
–40°C to +85°C
Automotive
–40°C to +125°C
Electrical Characteristics Over the Operating Range[9, 10]
Parameter
Description
Test Conditions
Min.
Max.
Unit
VDD
Power Supply Voltage
3.135
3.6
V
VDDQ
I/O Supply Voltage
2.375
VDD
V
VOH
Output HIGH Voltage
for 3.3V I/O, IOH = –4.0 mA
2.4
V
for 2.5V I/O, IOH = –1.0 mA
2.0
V
VOL
Output LOW Voltage
for 3.3V I/O, IOL = 8.0 mA
0.4
V
for 2.5V I/O, IOL = 1.0 mA
0.4
V
VIH
Input HIGH Voltage[9]
for 3.3V I/O
2.0
VDD + 0.3V V
for 2.5V I/O
1.7
VDD + 0.3V V
VIL
Input LOW Voltage[9]
for 3.3V I/O
–0.3
0.8
V
for 2.5V I/O
–0.3
0.7
V
IX
Input Leakage Current
except ZZ and MODE
GND
≤ V
I ≤ VDDQ
–5
5
A
Input Current of MODE Input = VSS
–30
A
Input = VDD
5
A
Input Current of ZZ
Input = VSS
–5
A
Input = VDD
30
A
IOZ
Output Leakage Current GND
≤ V
I ≤ VDDQ, Output Disabled
–5
5
A
IDD
VDD Operating Supply
Current
VDD = Max., IOUT = 0 mA,
f = fMAX = 1/tCYC
4-ns cycle, 250 MHz
325
mA
5-ns cycle, 200 MHz
265
mA
6-ns cycle, 166 MHz
240
mA
7.5-ns cycle, 133 MHz
225
mA
ISB1
Automatic CE
Power-down
Current—TTL Inputs
VDD = Max, Device Deselected,
VIN ≥ VIH or VIN ≤ VIL
f = fMAX = 1/tCYC
4-ns cycle, 250 MHz
120
mA
5-ns cycle, 200 MHz
110
mA
6-ns cycle, 166 MHz
100
mA
Industrial/
Commercial
7.5-ns cycle, 133 MHz
90
mA
Automotive 7.5-ns cycle, 133 MHz
115
mA
ISB2
Automatic CE
Power-down
Current—CMOS Inputs
VDD = Max, Device Deselected,
VIN ≤ 0.3V or VIN > VDDQ – 0.3V,
f = 0
All speeds
40
mA
Notes:
9. Overshoot: VIH(AC) < VDD +1.5V (Pulse width less than tCYC/2), undershoot: VIL(AC) > –2V (Pulse width less than tCYC/2).
10. TPower-up: Assumes a linear ramp from 0V to VDD(min.) within 200 ms. During this time VIH < VDD and VDDQ < VDD.
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