參數(shù)資料
型號: CY7C1512JV18-267BZXC
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: SRAM
英文描述: 4M X 18 QDR SRAM, 0.45 ns, PBGA165
封裝: 15 X 17 MM, 1.40 MM HEIGHT, LEAD FREE, MO-216, FBGA-165
文件頁數(shù): 2/26頁
文件大?。?/td> 648K
代理商: CY7C1512JV18-267BZXC
CY7C1510JV18, CY7C1525JV18
CY7C1512JV18, CY7C1514JV18
Document #: 001-14435 Rev. *F
Page 10 of 26
Truth Table
The truth table for CY7C1510JV18, CY7C1525JV18, CY7C1512JV18, and CY7C1514JV18 follows. [2, 3, 4, 5, 6, 7]
Operation
K
RPS WPS
DQ
Write Cycle:
Load address on the rising edge of K;
input write data on K and K rising edges.
L-H
X
L
D(A + 0) at K(t)
D(A + 1) at K(t)
Read Cycle:
Load address on the rising edge of K;
wait one and a half cycle; read data on C and C rising edges.
L-H
L
X
Q(A + 0) at C(t + 1)
↑ Q(A + 1) at C(t + 2) ↑
NOP: No Operation
L-H
H
D = X
Q = High-Z
D = X
Q = High-Z
Standby: Clock Stopped
Stopped
X
Previous State
Write Cycle Descriptions
The write cycle description table for CY7C1510JV18 and CY7C1512JV18 follows. [2, 8]
BWS0/
NWS0
BWS1/
NWS1
K
Comments
L
L–H
During the data portion of a write sequence
:
CY7C1510JV18
both nibbles (D
[7:0]) are written into the device.
CY7C1512JV18
both bytes (D
[17:0]) are written into the device.
L
L-H During the data portion of a write sequence
:
CY7C1510JV18
both nibbles (D
[7:0]) are written into the device.
CY7C1512JV18
both bytes (D
[17:0]) are written into the device.
L
H
L–H
During the data portion of a write sequence
:
CY7C1510JV18
only the lower nibble (D
[3:0]) is written into the device, D[7:4] remains unaltered.
CY7C1512JV18
only the lower byte (D
[8:0]) is written into the device, D[17:9] remains unaltered.
L
H
L–H During the data portion of a write sequence
:
CY7C1510JV18
only the lower nibble (D
[3:0]) is written into the device, D[7:4] remains unaltered.
CY7C1512JV18
only the lower byte (D
[8:0]) is written into the device, D[17:9] remains unaltered.
H
L
L–H
During the data portion of a write sequence
:
CY7C1510JV18
only the upper nibble (D
[7:4]) is written into the device, D[3:0] remains unaltered.
CY7C1512JV18
only the upper byte (D
[17:9]) is written into the device, D[8:0] remains unaltered.
H
L
L–H During the data portion of a write sequence
:
CY7C1510JV18
only the upper nibble (D
[7:4]) is written into the device, D[3:0] remains unaltered.
CY7C1512JV18
only the upper byte (D
[17:9]) is written into the device, D[8:0] remains unaltered.
H
L–H
No data is written into the devices during this portion of a write operation.
H
L–H No data is written into the devices during this portion of a write operation.
Notes
2. X = “Don't Care,” H = Logic HIGH, L = Logic LOW,
represents rising edge.
3. Device powers up deselected with the outputs in a tri-state condition.
4. “A” represents address location latched by the devices when transaction was initiated. A + 0, A + 1 represents the internal address sequence in the burst.
5. “t” represents the cycle at which a Read/Write operation is started. t + 1, and t + 2 are the first, and second clock cycles respectively succeeding the “t” clock cycle.
6. Data inputs are registered at K and K rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode.
7. It is recommended that K = K and C = C = HIGH when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line charging
symmetrically.
8. Is based on a write cycle that was initiated in accordance with the Write Cycle Descriptions table. NWS0, NWS1,BWS0, BWS1,BWS2 and BWS3 can be altered on
different portions of a write cycle, as long as the setup and hold requirements are achieved.
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