- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄298975 > CY7C1524KV18-333BZI (CYPRESS SEMICONDUCTOR CORP) 2M X 36 DDR SRAM, 0.45 ns, PBGA165 PDF資料下載
參數(shù)資料
| 型號(hào)： | CY7C1524KV18-333BZI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | SRAM |
| 英文描述： | 2M X 36 DDR SRAM, 0.45 ns, PBGA165 |
| 封裝： | 15 X 13 MM, 1.40 MM HEIGHT, MO-216, FBGA-165 |
| 文件頁數(shù)： | 1/32頁 |
| 文件大?。?/td> | 883K |
| 代理商： | CY7C1524KV18-333BZI |
當(dāng)前第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁
72-Mbit DDR II SIO SRAM 2-Word
Burst Architecture
CY7C1522KV18, CY7C1529KV18
CY7C1523KV18, CY7C1524KV18
Cypress Semiconductor Corporation
198 Champion Court
San Jose
, CA 95134-1709
408-943-2600
Document Number: 001-00438 Rev. *F
Revised January 29, 2010
Features
■ 72 Mbit Density (8M x 8, 8M x 9, 4M x 18, 2M x 36)
■ 333 MHz Clock for High Bandwidth
■ 2-word Burst for reducing Address Bus Frequency
■ Double Data Rate (DDR) Interfaces
(data transferred at 666 MHz) at 333 MHz
■ Two Input Clocks (K and K) for precise DDR Timing
SRAM uses rising edges only
■ Two Input Clocks for Output Data (C and C) to minimize Clock
Skew and Flight Time mismatches
■ Echo Clocks (CQ and CQ) simplify Data Capture in High Speed
Systems
■ Synchronous Internally Self timed Writes
■ DDR II operates with 1.5 Cycle Read Latency when DOFF is
asserted HIGH
■ Operates similar to DDR-I Device with 1 Cycle Read Latency
when DOFF is asserted LOW
■ 1.8V Core Power Supply with HSTL Inputs and Outputs
■ Variable Drive HSTL Output Buffers
■ Expanded HSTL Output Voltage (1.4V–VDD)
Supports both 1.5V and 1.8V IO supply
■ Available in 165-ball FBGA Package (13 x 15 x 1.4 mm)
■ Offered in both Pb-free and non Pb-free Packages
■ JTAG 1149.1 compatible Test Access Port
■ Phase Locked Loop (PLL) for accurate Data Placement
Configurations
CY7C1522KV18 – 8M x 8
CY7C1529KV18 – 8M x 9
CY7C1523KV18 – 4M x 18
CY7C1524KV18 – 2M x 36
Functional Description
The CY7C1522KV18, CY7C1529KV18, CY7C1523KV18, and
CY7C1524KV18 are 1.8V Synchronous Pipelined SRAMs,
equipped with DDR II SIO (Double Data Rate Separate I/O)
architecture. The DDR II SIO consists of two separate ports: the
read port and the write port to access the memory array. The
read port has data outputs to support read operations and the
write port has data inputs to support write operations. The DDR
II SIO has separate data inputs and data outputs to completely
eliminate the need to “turnaround” the data bus required with
common I/O devices. Access to each port is accomplished
through a common address bus. Addresses for read and write
are latched on alternate rising edges of the input (K) clock. Write
data is registered on the rising edges of both K and K. Read data
is driven on the rising edges of C and C if provided, or on the
rising edge of K and K if C/C are not provided. Each address
location is associated with two 8-bit words in the case of
CY7C1522KV18,
two
9-bit
words
in
the
case
of
CY7C1529KV18,
two
18-bit
words
in
the
case
of
CY7C1523KV18, and two 36-bit words in the case of
CY7C1524KV18 that burst sequentially into or out of the device.
Asynchronous inputs include an output impedance matching
input (ZQ). Synchronous data outputs are tightly matched to the
two output echo clocks CQ/CQ, eliminating the need to capture
data separately from each individual DDR II SIO SRAM in the
system design. Output data clocks (C/C) enable maximum
system clocking and data synchronization flexibility.
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the C or C (or K or K in a single clock
domain) input clocks. Writes are conducted with on-chip
synchronous self-timed write circuitry.
Table 1. Selection Guide
Description
333 MHz
300 MHz
250 MHz
200 MHz
167 MHz
Unit
Maximum Operating Frequency
333
300
250
200
167
MHz
Maximum Operating Current
x8
510
480
420
370
340
mA
x9
510
480
420
370
340
x18
520
490
430
380
340
x36
640
600
530
450
400
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C1612KV18-333BZXC | 8M X 18 QDR SRAM, PBGA165 |
| CY7C256-45PC | 32K X 8 OTPROM, 45 ns, PDIP28 |
| CY7C2561KV18-450BZC | 8M X 8 QDR SRAM, 0.37 ns, PBGA165 |
| CY7C2566KV18-450BZI | 8M X 8 DDR SRAM, 0.37 ns, PBGA165 |
| CY7C293AL-35WC | 2K X 8 UVPROM, 35 ns, CDIP24 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C1525JV18250BZC | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1525JV18-250BZC | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 8M x 9 1.8V QDR-II 靜態(tài)隨機(jī)存取存儲(chǔ)器 Two-Word Burst RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1525JV18-250BZCES | 制造商:Rochester Electronics LLC 功能描述: 制造商:Cypress Semiconductor 功能描述: |
| CY7C1525JV18-250BZXC | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 8M x 9 1.8V QDR-II 靜態(tài)隨機(jī)存取存儲(chǔ)器 Two-Word Burst RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1525KV18-250BZC | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 72MB (8Mx9) 1.8v 250MHz QDR II 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。