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參數(shù)資料
| 型號(hào)： | CY7C1524KV18-333BZI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | SRAM |
| 英文描述： | 2M X 36 DDR SRAM, 0.45 ns, PBGA165 |
| 封裝： | 15 X 13 MM, 1.40 MM HEIGHT, MO-216, FBGA-165 |
| 文件頁數(shù)： | 30/32頁 |
| 文件大?。?/td> | 883K |
| 代理商： | CY7C1524KV18-333BZI |
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CY7C1522KV18, CY7C1529KV18
CY7C1523KV18, CY7C1524KV18
Document Number: 001-00438 Rev. *F
Page 7 of 32
Pin Definitions
Pin Name
I/O
Pin Description
D[x:0]
Input-
Synchronous
Data Input Signals. Sampled on the rising edge of K and K clocks during valid write operations.
CY7C1522KV18 - D[7:0]
CY7C1529KV18 - D[8:0]
CY7C1523KV18 - D[17:0]
CY7C1524KV18 - D[35:0]
LD
Input-
Synchronous
Synchronous Load. This input is brought LOW when a bus cycle sequence is defined. This definition
includes address and read/write direction. All transactions operate on a burst of 2 data (one clock period
of bus activity).
NWS0,
NWS1
Nibble Write Select 0, 1
Active LOW (CY7C1522KV18 Only). Sampled on the rising edge of the K
and K clocks during Write operations. Used to select which nibble is written into the device during the
current portion of the Write operations.Nibbles not written remain unaltered.
NWS0 controls D[3:0] and NWS1 controls D[7:4].
All Nibble Write Selects are sampled on the same edge as the data. Deselecting a Nibble Write Select
ignores the corresponding nibble of data and it is not written into the device.
BWS0,
BWS1,
BWS2,
BWS3
Input-
Synchronous
Byte Write Select 0, 1, 2, and 3
Active LOW. Sampled on the rising edge of the K and K clocks during
write operations. Used to select which byte is written into the device during the current portion of the write
operations. Bytes not written remain unaltered.
CY7C1529KV18
BWS0 controls D[8:0]
CY7C1523KV18
BWS0 controls D[8:0], BWS1 controls D[17:9].
CY7C1524KV18
BWS0 controls D[8:0], BWS1 controls D[17:9],BWS2 controls D[26:18] and BWS3 controls
D[35:27].
All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write Select
ignores the corresponding byte of data and it is not written into the device.
A
Input-
Synchronous
Address Inputs. Sampled on the rising edge of the K clock during active read and write operations. These
address inputs are multiplexed for both read and write operations. Internally, the device is organized as
8M x 8 (2 arrays each of 4M x 8) for CY7C1522KV18, 8M x 9 (2 arrays each of 4M x 9) for CY7C1529KV18,
4M x 18 (2 arrays each of 2M x 18) for CY7C1523KV18 and 2M x 36 (2 arrays each of 1M x 36) for
CY7C1524KV18. Therefore, only 22 address inputs are needed to access the entire memory array of
CY7C1522KV18 and CY7C1529KV18, 21 address inputs for CY7C1523KV18 and 20 address inputs for
CY7C1524KV18. These inputs are ignored when the appropriate port is deselected.
Q[x:0]
Outputs-
Synchronous
Data Output Signals. These pins drive out the requested data during a read operation. Valid data is
driven out on the rising edge of both the C and C clocks during read operations, or K and K when in single
clock mode. When the read port is deselected, Q[x:0] are automatically tristated.
CY7C1522KV18
Q[7:0]
CY7C1529KV18
Q[8:0]
CY7C1523KV18
Q[17:0]
CY7C1524KV18
Q[35:0]
R/W
Input-
Synchronous
Synchronous Read/Write Input. When LD is LOW, this input designates the access type (read when
R/W is HIGH, write when R/W is LOW) for the loaded address. R/W must meet the setup and hold times
around the edge of K.
C
Input Clock
Positive Input Clock for Output Data. C is used in conjunction with C to clock out the read data from
the device. C and C can be used together to deskew the flight times of various devices on the board back
to the controller. See Application Example on page 10 for further details.
C
Input Clock
Negative Input Clock for Output Data. C is used in conjunction with C to clock out the read data from
the device. C and C can be used together to deskew the flight times of various devices on the board back
to the controller. See Application Example on page 10 for further details.
K
Input Clock
Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the device
and to drive out data through Q[x:0] when in single clock mode. All accesses are initiated on the rising
edge of K.
K
Input Clock
Negative Input Clock Input. K is used to capture synchronous inputs being presented to the device and
to drive out data through Q[x:0] when in single clock mode.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C1525JV18250BZC | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1525JV18-250BZC | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 8M x 9 1.8V QDR-II 靜態(tài)隨機(jī)存取存儲(chǔ)器 Two-Word Burst RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1525JV18-250BZCES | 制造商:Rochester Electronics LLC 功能描述: 制造商:Cypress Semiconductor 功能描述: |
| CY7C1525JV18-250BZXC | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 8M x 9 1.8V QDR-II 靜態(tài)隨機(jī)存取存儲(chǔ)器 Two-Word Burst RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1525KV18-250BZC | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 72MB (8Mx9) 1.8v 250MHz QDR II 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
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