參數(shù)資料
型號(hào)： CY7C1524KV18-333BZI
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： SRAM
英文描述： 2M X 36 DDR SRAM, 0.45 ns, PBGA165
封裝： 15 X 13 MM, 1.40 MM HEIGHT, MO-216, FBGA-165
文件頁(yè)數(shù)： 18/32頁(yè)
文件大?。?/td> 883K
代理商： CY7C1524KV18-333BZI
CY7C1522KV18, CY7C1529KV18
CY7C1523KV18, CY7C1524KV18
Document Number: 001-00438 Rev. *F
Page 25 of 32
Output Times
tCO
tCHQV
C/C Clock Rise (or K/K in single
clock mode) to Data Valid
–
0.45
–
0.45
–
0.45
–
0.45
–
0.50
ns
tDOH
tCHQX
Data Output Hold after Output C/C
Clock Rise (Active to Active)
–0.45
–
–0.45
–
–0.45
–
–0.45
–
–0.50
–
ns
tCCQO
tCHCQV
C/C Clock Rise to Echo Clock Valid
–
0.45
–
0.45
–
0.45
–
0.45
–
0.50
ns
tCQOH
tCHCQX
Echo Clock Hold after C/C Clock
Rise
–0.45
–
–0.45
–
–0.45
–
–0.45
–
–0.50
–
ns
tCQD
tCQHQV
Echo Clock High to Data Valid
0.25
0.27
0.30
0.35
0.40
ns
tCQDOH
tCQHQX
Echo Clock High to Data Invalid
–0.25
–
–0.27
–
–0.30
–
–0.35
–
–0.40
–
ns
tCQH
tCQHCQL
Output Clock (CQ/CQ) HIGH [23]
1.25
–1.40–
1.75–2.25
–
2.75
–
ns
tCQHCQH tCQHCQH
CQ Clock Rise to CQ Clock Rise
(rising edge to rising edge) [23]
1.25
–1.40–
1.75–2.25
–
2.75
–
ns
tCHZ
tCHQZ
Clock (C/C) Rise to High-Z
(Active to High-Z) [24, 25]
–
0.45
–
0.45
–
0.45
–
0.45
–
0.50
ns
tCLZ
tCHQX1
Clock (C/C) Rise to Low-Z [24, 25]
–0.45
–
–0.45
–
–0.45
–
–0.45
–
–0.50
–
ns
PLL Timing
tKC Var
Clock Phase Jitter
–
0.20
–
0.20
–
0.20
–
0.20
–
0.20
ns
tKC lock
PLL Lock Time (K, C)
20
–20–20–20–
20
–
μs
tKC Reset
K Static to PLL Reset
30
ns
Switching Characteristics (continued)
Over the Operating Range [20, 21]
Cypress
Parameter
Consortium
Parameter
Description
333 MHz
300 MHz
250 MHz
200 MHz
167 MHz
Unit
Min Max Min Max Min Max Min Max Min Max
Notes
23. These parameters are extrapolated from the input timing parameters (tCYC/2 - 250 ps, where 250 ps is the internal jitter). These parameters are only guaranteed by
design and are not tested in production
24. tCHZ, tCLZ, are specified with a load capacitance of 5 pF as in (b) of AC Test Loads and Waveforms. Transition is measured ± 100 mV from steady-state voltage.
25. At any voltage and temperature tCHZ is less than tCLZ and tCHZ less than tCO.
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參數(shù)描述
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CY7C1525JV18-250BZCES 制造商:Rochester Electronics LLC 功能描述: 制造商:Cypress Semiconductor 功能描述:
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CY7C1525KV18-250BZC 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 72MB (8Mx9) 1.8v 250MHz QDR II 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
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