參數(shù)資料
型號(hào): CY7C1524KV18-333BZI
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類(lèi): SRAM
英文描述: 2M X 36 DDR SRAM, 0.45 ns, PBGA165
封裝: 15 X 13 MM, 1.40 MM HEIGHT, MO-216, FBGA-165
文件頁(yè)數(shù): 8/32頁(yè)
文件大?。?/td> 883K
代理商: CY7C1524KV18-333BZI
CY7C1522KV18, CY7C1529KV18
CY7C1523KV18, CY7C1524KV18
Document Number: 001-00438 Rev. *F
Page 16 of 32
TAP Controller Block Diagram
TAP Electrical Characteristics
Over the Operating Range [10, 11, 12]
Parameter
Description
Test Conditions
Min
Max
Unit
VOH1
Output HIGH Voltage
IOH = 2.0 mA
1.4
V
VOH2
Output HIGH Voltage
IOH = 100 μA1.6
V
VOL1
Output LOW Voltage
IOL = 2.0 mA
0.4
V
VOL2
Output LOW Voltage
IOL = 100 μA0.2
V
VIH
Input HIGH Voltage
0.65VDD VDD + 0.3
V
VIL
Input LOW Voltage
–0.3
0.35VDD
V
IX
Input and Output Load Current
GND
≤ VI ≤ VDD
–5
5
μA
0
1
2
.
29
30
31
Boundary Scan Register
Identification Register
0
1
2
.
108
0
1
2
Instruction Register
Bypass Register
Selection
Circuitry
Selection
Circuitry
TAP Controller
TDI
TDO
TCK
TMS
Notes
10. These characteristics pertain to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in the Electrical Characteristics table.
11. Overshoot: VIH(AC) < VDDQ + 0.85V (Pulse width less than tCYC/2), Undershoot: VIL(AC) > 1.5V (Pulse width less than tCYC/2).
12. All Voltage referenced to Ground.
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