參數資料
型號: DDP3310B
廠商: MICRONAS SEMICONDUCTOR HOLDING AG
元件分類: 消費家電
英文描述: Display and Deflection Processor
中文描述: SPECIALTY CONSUMER CIRCUIT, PQCC68
封裝: PLASTIC, LCC-68
文件頁數: 23/60頁
文件大?。?/td> 1540K
代理商: DDP3310B
ADVANCE INFORMATION
DDP 3310B
Micronas
23
Table 3
2:
I
2
C Control Registers
I
2
C Control and Status Registers
Subaddr.
Mode
Function
Default
Name
XDFP INTERFACE
h
13
16-w
XDFP read address
bit[[9:0]
bit[15:10]
10-bit XDFP RAM address
reserved, set to zero
0
DFPRD
h
12
16-w
XDFP write address
bit[[9:0]
bit[15:10]
10-bit XDFP RAM address
reserved, set to zero
DFPWR
ANALOG FAST-BLANK MONITOR
h
1E
8-r
Fast-Blank signal status
bit[0]
bit[1]
bit[7:2]
0/1
FBLIN level Low/High
FBLIN slope: 1 = falling edge occurred
not used
FBLSTAT
FBLEV
FBSLO
h
11
16-r/w
picture frame color, 12 bit wide
bit[3:0]
0..15
bit[7:4]
0..15
bit[11:8]
0..15
bit[15:12]
0
blue amplitude
green amplitude
red amplitude
not used
0
0
0
0
PFC
PFCB
PFCG
PFCR
OUTPUT PINS
h
10
8-r/w
output pin configuration
bit[2:0]
pin driver strength, FIFO control
7 = output tristate
6 = minimum strength
0 = maximum strength
0/1
strong/weak driver strength PWM1
0/1
strong/weak driver strength PWM2
0/1
disable/enable internal resistor for vertical
and East/West drive output
0/1
High/Low-active horizontal flyback input
0/1
disable/enable following I/O pin:
FIFO -controll signals, PWM1&2, HCS,
R/G/BIN2, and VS2.
bit[3]
bit[4]
bit[5]
bit[6]
bit[7]
0
0
0
0
0
0
PSTR
PSTSY
PSTPR1
PSTPR2
VEWXR
FLYPOL
OSDOFF
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