參數資料
型號: DDP3310B
廠商: MICRONAS SEMICONDUCTOR HOLDING AG
元件分類: 消費家電
英文描述: Display and Deflection Processor
中文描述: SPECIALTY CONSUMER CIRCUIT, PQCC68
封裝: PLASTIC, LCC-68
文件頁數: 32/60頁
文件大?。?/td> 1540K
代理商: DDP3310B
DDP 3310B
ADVANCE INFORMATION
32
Micronas
VERTICAL PARAMETERS
h
152
16-r/w
bit [6:0]
0... 127
window (LPFD
±
VSYNWIN) for sync
detection
32
VSYNWIN
h
153
16-r/w
bit [9:0]
0... 1023
lines per field
312
LPFD
h
154
16-r/w
bit [9:0]
0... 1023
number of hold lines
10
HOLDL
h
155
16-r/w
bit [9:0]
0... 1023
number of flyback lines
(flyback booster active)
5
FLYBL
VERTICAL SAWTOOTH CORRECTION (%-values according to DAC range)
h
14D
16-r/w
bit [15:8]
128...127 vertical amplitude (
±
25 %)
0
AMPL
h
14E
16-r/w
bit [14:6]
0...510
zoom (0...100...200 %)
256
ZOOM
h
14F
16-r/w
bit [15:8]
128...127 vertical picture position (
±
50 %)
(DC offset of Sawtooth output). This offset
is independent of EHT compensation.
0
VPOS
h
150
16-r/w
bit [15:8]
128...127 linearity (
±
10 %)
0
LIN
h
151
16-r/w
bit [15:8]
128...127 S-correction (
±
8 %)
0
SCORR
EAST-WEST PARABOLA (%-values according to DAC range)
h
157
16-r/w
bit [15:7]
256..255
picture width (0...100 %)
51
WIDTH
h
158
16-r/w
bit [15:8]
128...127 trapez correction (
±
100 %)
0
TCORR
h
159
16-r/w
bit [15:8]
128...127 cushion correction (
±
100 %)
0
CUSH
h
15A
16-r/w
bit [15:8]
128...127 upper corner correction (
±
100 %)
0
CRNU
h
15B
16-r/w
bit [15:8]
128...127 lower corner correction (
±
100 %)
0
CRNL
EXTREME HIGH-TENSION (EHT) COMPENSATION (%-values according to DAC range)
h
148
16-r/w
bit[15:6]
512...511 EHT compensation coefficient for
horizontal phase (
±
1.5
μ
s)
0
EHTHP
h
149
16-r/w
bit[14:6]
0...511
EHT time constant for horizontal phase
compensation
0 = off
0
EHTH_TC
h
147
16-r/w
bit[15:6]
512...511 EHT compensation coefficient for
horizontal amplitude (
±
100 %)
0
EHTH
h
15C
16-r/w
bit [15:6]
512...511 EHT compensation coefficient for
vertical amplitude (
±
25 %)
0
EHTV
h
15D
16-r/w
bit [14:6]
0...511
time constant for control of vertical and
horizontal amplitude EHT compensation
0 = off
0
EHTV_TC
Table 3
3:
Control Registers of the XDFP, continued
XDFP Control and Status Registers
Subaddr.
Mode
Function
Default
Name
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