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參數(shù)資料
| 型號(hào)： | DDP3310B |
| 廠商： | MICRONAS SEMICONDUCTOR HOLDING AG |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | Display and Deflection Processor |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQCC68 |
| 封裝： | PLASTIC, LCC-68 |
| 文件頁數(shù)： | 30/60頁 |
| 文件大小： | 1540K |
| 代理商： | DDP3310B |
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DDP 3310B
ADVANCE INFORMATION
30
Micronas
DISPLAY FREQUENCY DOUBLING
h
’
176
16-r/w
display frequency doubling control word
bit[1:0]
display raster mode (A
’
= field A in raster B)
0 = A A
‘
B
‘
B
1 = A A B B
2 = A A B
‘
B
‘
3=not used
bit[3:2]
minimum field length filter
0 = off
1 = 2 fields
2 = 3 fields
3 = 4 fields
bit[5:4]
input sync doubling switch
0 = leave H and V sync unchanged
1 = double VSYNC and leave HSYNC unchanged
2 = double HSYNC and leave VSYNC unchanged
3 = double H and V sync
bit[6]
clock switch
0 = Clock from LLC2 pin divided by 2
1 = Clock from LLC1 pin
bit[7]
test bit, set to 0
bit[8]
0
automatic VS/VS2 polarity detection
1
Low-active VS/VS2 input
bit[9]
0 / 1
High/Low-active HS input
bit[10]
0 / 1
VS / VS2 Pin is source of VSYNC
bit[11]
0 / 1
dis-/enable still picture (only available if
display frequency doubling is enabled)
bit[12]
0 / 1
High / Low-active FIFO controll signals
0
0
0
0
0
0
0
0
0
0
DFDCTRL
DFDMODE
DFDFILT
DFDSW
DFDCLK
VSYPOL
HSYPOL
VSYSRC
STILL
FIFOPOL
TIMING
h
’
1A4
16-r/w
vertical blanking start
bit [8:0]
0..511
first line of vertical blanking (+ 128 offset)
182
VBST
h
’
1A0
16-r/w
vertical blanking stop
bit [8:0]
0..511
last line of vertical blanking
22
VBSO
h
’
1D3
16-r/w
bit[10:0]
0..1295
horizontal blanking start
(see Table 2
–
5 for max. pixels per line)
253
HBST
h
’
1D4
16-r/w
bit[10:0]
0..1295
horizontal blanking stop
(see Table 2
–
5 for max. pixels per line)
331
HBSO
h
’
1D2
16-r/w
bit[10:0]
0..1295
Start at active video relative to pixel
counter.
(see Table 2
–
5 for max. pixels per line)
330
NEWLIN
h
’
18b
16-r/w
bit [8:0]
0...511
start point of active video relative to incom-
ing HS signal in steps of 2 LLC2 clocks; can
be used e.g. for panning
0
SFIF
Table 3
–
3:
Control Registers of the XDFP, continued
XDFP Control and Status Registers
Subaddr.
Mode
Function
Default
Name
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DDR-TJS-T2 | LED AlInGaP |
| DD0-SJS-S1 | LED AlInGaP |
| DD0-SJS-S2 | LED AlInGaP |
| DD0-SJS-T1 | LED AlInGaP |
| DD0-SJS-T2 | LED AlInGaP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DDP-37CT | 制造商:Pan Pacific 功能描述: |
| DDP400-P1 | 制造商:CCM Assembly & Manufacturing 功能描述:AC Input Cable for ROAL DDP400 series, Bulk |
| DDP400-P4 | 制造商:CCM Assembly & Manufacturing 功能描述:DC Output Cable for ROAL DDP400 series, Bulk |
| DDP400-P6 | 制造商:CCM Assembly & Manufacturing 功能描述:Signal Cable for ROAL DDP400 series, Bulk |
| DDP400-US12-FF | 制造商:ROAL Electronics 功能描述:AC/DC 400W 12V Single Output Enclosed Front Fan, Bulk |
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