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參數(shù)資料
| 型號： | DDP3310B |
| 廠商： | MICRONAS SEMICONDUCTOR HOLDING AG |
| 元件分類： | 消費家電 |
| 英文描述： | Display and Deflection Processor |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQCC68 |
| 封裝： | PLASTIC, LCC-68 |
| 文件頁數(shù)： | 39/60頁 |
| 文件大?。?/td> | 1540K |
| 代理商： | DDP3310B |
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ADVANCE INFORMATION
DDP 3310B
Micronas
39
Pin 22
–
DAC Current Reference
XREF
(Fig. 4
–
13)
External reference resistor for DAC output currents,
typical 10 k
, to adjust the output current of the D/A
converters. (see recommended operating conditions).
This resistor has to be connected to analog ground as
closely as possible to the pin.
Pin 23
–
Scan Velocity Modulation Output
SVM
(Fig. 4
–
14)
This output delivers the analog SVM signal (see Sec-
tion 2.1.11.). The D/A converter is a current sink like
the RGB D/A converters. At zero signal the output cur-
rent is 50 % of the maximum output current.
Pin 24, 25, 26
–
Analog RGB Output
ROUT, GOUT,
BOUT
(Fig. 4
–
14)
These pins are the analog Red/Green/Blue outputs of
the back-end. The outputs are current sinks.
Pin 27
–
Ground, Analog Back-end
GNDO*
This pin has to be connected to the analog ground. No
supply current for the digital stages should flow
through this line.
Pin 28
–
Supply Voltage, Analog Back-end
VSUPO*
This pin has to be connected to the analog supply volt-
age. No supply current for the digital stages should
flow through this line.
Pin 29
–
DAC Reference Decoupling/Beam Current
Safety
VRD/BCS
(Fig. 4
–
13)
Via this pin, the DAC reference voltage is decoupled by
an external capacitor. The DAC output currents
depend on this voltage, therefore a pull-down transis-
tor can be used to shut off all beam currents. A decou-
pling capacitor of 4.7
μ
F in parallel to 100 nF (low
inductance) is required.
Pin 30, 34
–
Fast-Blank Input
FBLIN1/2
(Fig. 4
–
7)
These pins are used to switch the RGB outputs to the
external analog RGB inputs. FBLIN1 switches the
RIN1, GIN1 and BIN1 inputs, FBLIN2 switches the
RIN2, GIN2 and BIN2 inputs. The active level (Low or
High) can be selected by software.
Pin 31, 32, 33
–
Analog RGB Input1
RIN1, GIN1, BIN1
(Fig. 4
–
15)
These pins are used to insert an external analog RGB
signal, e.g. from a SCART connector which can by
switched to the analog RGB outputs with the Fast-
Blank signal. The analog back-end provides separate
brightness and contrast settings for the external ana-
log RGB signals (see Section 2.2.1. and Fig. ).
Pin 35, 36, 37
–
Analog RGB Input2
RIN2, GIN2, BIN2
(Fig. 4
–
15)
These pins are used to insert an external analog RGB
signal, e.g. from a SCART connector which can by
switched to the analog RGB outputs with the Fast-
Blank signal. The analog back-end provides separate
brightness and contrast settings for the external ana-
log RGB signals (see Section 2.2.1. and Fig. ).
Pin 38
–
Test Input
TEST
(Fig. 4
–
16)
This pin enables factory test modes. For normal opera-
tion it must be connected to ground.
Pin 39
–
Reset Input
RESQ
(Fig. 4
–
16)
A low level on this pin resets the DDP 3310B.
Pin 40
–
Adjustable DC Output 1
PWM1
(Fig. 4
–
17)
This output delivers a DC voltage with a resolution of
8 bit, adjustable over the I
2
C bus. The output is driven
by a push-pull stage. The PWM frequency is appr.
79.4 kHz. For a ripple-free voltage a first order lowpass
filter with a corner frequency <120 Hz should be
applied.
Pin 41
–
Adjustable DC Output 2
PWM2
(Fig. 4
–
17)
See pin 40.
Pin 42
–
Half-Contrast Input
HCS
(Fig. 4
–
18)
Via this input pin the output level of the D/A-converted
internal RGB signals can be reduced by 6 dB. Inserted
external analog RGB signals remain unchanged.
Pin 43...50
–
Picture Bus Chroma
C0...C7
(Fig. 4
–
3)
The Picture Bus Chroma lines carry the multiplexed
color component data. For the 4:1:1 input signal (4-bit
chroma) the pins C4...C7 are used.
Pin 51
–
Supply Voltage, Digital Circuitry
VSUPD*
Pin 52
–
Ground, Digital Circuitry
GNDD*
Digital Circuitry Input Reference
Pin 53
–
Main Clock Input
LLC2
(53)
(Fig. 4
–
16)
This is the input for the line-locked clock signal. The
frequency can be 27, 32, or 40.5 MHz.
Pin 54...61
–
Picture Bus Luma
Y0...Y7
(Fig. 4
–
3)
The Picture Bus Luma lines carry the digital luminance
data.
Pin 62
–
Line-Locked Clock Input
LLC1
(Fig. 4
–
16)
This is the reference clock for the single frequency
input sync signals required in a FIFO application. The
frequency can be 13.5, 16, or 20.25 MHz.
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