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參數(shù)資料
| 型號(hào)： | DDP3310B |
| 廠商： | MICRONAS SEMICONDUCTOR HOLDING AG |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | Display and Deflection Processor |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQCC68 |
| 封裝： | PLASTIC, LCC-68 |
| 文件頁(yè)數(shù)： | 24/60頁(yè) |
| 文件大小： | 1540K |
| 代理商： | DDP3310B |
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DDP 3310B
ADVANCE INFORMATION
24
Micronas
Table 3
–
3:
Control Registers of the XDFP
XDFP Control and Status Registers
Subaddr.
Mode
Function
Default
Name
INPUT FORMATTER
h
’
1B0
16-r/w
Input format
bit [0]
bit [1]
bit [2]
0/1
0/1
0/1
4:2:2 / 4:1:1 mode
binary offset / 2
‘
s complement
enable / disable blanking to black ( for luma
and chroma input when HS = 0 )
select color multiplex
bit [4:3]
0...3
1
1
1
0
INFMT
M411
COB
BLNK
CMUX
SCALER CONTROL REGISTER
h
’
1C1
16-r/w
scaler mode register
bit[1:0]
scaler mode
0
1
2
3
linear scaling mode
non-linear scaling mode,
’
panorama
’
non-linear scaling mode,
’
waterglass
’
reserved
reserved, set to 0
reserved, set to 0
scaler update command, set to 1 to update
only scaler mode register
scaler update command, set to 1 to update
all scaler control registers
bit[2]
bit[13:3]
bit[14]
0
bit[15]
0
0
0
0
SCMODE
PANO
SCMODUP
SCUPDATE
h
’
1C2
16-r/w
active video length for 1-h FIFO
bit[11:0]
0...1295
720
length in pixels
LLC mode (864/h)
720
FFLIM
h
’
1C3
16-r/w
scaler1 coefficient; this scaler compresses the signal.
bit[11:0]
1024..4095 compression by a factor c,
the value c*1024 is required
1024
SCINC1
h
’
1C4
16-r/w
scaler2 coefficient; this scaler expands the signal.
bit[11:0]
256..1024
expansion by a factor c,
the value 1/c*1024 is required
682
SCINC2
h
’
1C5
16-r/w
bit[11:0]
0...4095
scaler1/2 non-linear scaling coefficient
0
SCINC
h
’
1C6
...
h
’
1CA
16-r/w
scaler1 window controls (see Table 3
–
4)
bit[11:0]
0...4095
5 registers for control of the non-linear
scaling
0
...
0
SCW1_1
...
SCW1_5
h
’
1CB
...
h
’
1CF
16-r/w
scaler2 window controls (see Table 3
–
4)
bit[11:0]
0...4095
5 registers for control of the non-linear
scaling
0
...
0
SCW2_1
...
SCW2_5
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