參數(shù)資料
型號(hào): DDP3310B
廠商: MICRONAS SEMICONDUCTOR HOLDING AG
元件分類(lèi): 消費(fèi)家電
英文描述: Display and Deflection Processor
中文描述: SPECIALTY CONSUMER CIRCUIT, PQCC68
封裝: PLASTIC, LCC-68
文件頁(yè)數(shù): 33/60頁(yè)
文件大?。?/td> 1540K
代理商: DDP3310B
ADVANCE INFORMATION
DDP 3310B
Micronas
33
ANALOG RGB INSERTION
h
17A
16-r/w
Fast-Blank interface mode
bit [0]
0
1
bit [1]
0/1
bit [2]
0
1
bit[3]
0
1
bit [4]
0
1
bit [5]
0
1
bit[6]
0/1
bit[7]
0/1
bit[8]
0/1
Fast-Blank from FBLIN1 pin
force internal Fast-Blank signal to High
Fast-Blank active High/Low at FBLIN pin
Fast-Blank from FBLIN1 pin
force internal Fast-Blank signal to Low
Fast-Blank priority
FBLIN1>FBLIN2
FBLIN1<FBLIN2
Fast-Blank from FBLIN2 pin
force internal Fast-Blank signal to Low
Fast-Blank from FBLIN2 pin
force internal Fast-Blank signal to High
Fast-Blank monitor input select FBLIN1/2
disable/enable clamping for RGBIN1&2
half contrast signal active High/Low
at HCS pin
disable/enable half contrast switching
half contrast signal from HCS pin
force internal half contrast signal to High
clamp RGBIN1 to black (if CLAMP =1)
clamp RGBIN1 to bias (if CLAMP =1)
clamp RGBIN2 to black (if CLAMP =1)
clamp RGBIN2 to bias (if CLAMP =1)
bit[9]
bit[10]
0/1
0
1
0
1
0
1
bit[11]
bit[12]
0
0
0
0
0
0
0
0
0
0
0
0
0
FBLMODE
FBFOH1
FBPOL
FBFOL1
FBPRIO
FBFOL2
FBFOH2
FBMON
CLAMP
HCSPOL
HCSEN
HCSFOH
C1_B
C2_B
I
2
C-CONTROLLED 8-BIT PWM
h
178
16-r/w
bit[7:0]
0..255
PWM1 data word
0
PWM1
h
179
16-r/w
bit[7:0]
0..255
PWM2 data word
0
PWM2
XDFP STATUS REGISTER
h
0
16-r/w
firmware version number
bit[7:0]
bit[15:8]
firmware release
hardware version number (TC)
VER
FW_REL
HW_VER
Table 3
3:
Control Registers of the XDFP, continued
XDFP Control and Status Registers
Subaddr.
Mode
Function
Default
Name
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