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參數(shù)資料
| 型號(hào)： | DDP3310B |
| 廠商： | MICRONAS SEMICONDUCTOR HOLDING AG |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | Display and Deflection Processor |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQCC68 |
| 封裝： | PLASTIC, LCC-68 |
| 文件頁(yè)數(shù)： | 4/60頁(yè) |
| 文件大?。?/td> | 1540K |
| 代理商： | DDP3310B |
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DDP 3310B
ADVANCE INFORMATION
4
Micronas
Display and Deflection Processor
1. Introduction
The DDP 3310B is a single-chip digital Display and
Deflection Processor designed for high-quality back-
end applications in 100/120-Hz TV sets with 4:3- or
16:9 picture tubes. The IC can be combined with mem-
bers of the DIGIT 3000 IC family (VPC 32xx,
TPU 3040), or it can be used with third-party products.
The IC contains the entire digital video component and
deflection processing and all analog interface compo-
nents.
1.1. Main Features
Video processing
– linear horizontal scaling (0.25 … 4)
– non-linear horizontal scaling “panoramavision”
– dynamic peaking
– soft limiter (gamma correction)
– color transient improvement
– programmable RGB matrix
– picture frame generator
– two analog RGB/Fast-Blank inputs
Deflection processing
– scan velocity modulation output
– high-performance H/V deflection
– EHT compensation for vertical / East/West
– soft start/stop of H-Drive
– vertical angle and bow
– differential vertical output
– vertical zoom via deflection
– horizontal and vertical protection circuit
– adjustable horizontal frequency for VGA/SVGA dis-
play
Miscellaneous
– selectable 4:1:1/4:2:2 YC
r
C
b
input
– selectable 27/32-MHz line-locked clock input
– crystal oscillator for horizontal protection
– automatic picture tube adjustment (cutoff, white-
drive)
– single 5-V power supply
– hardware for simple 50/60-Hz to 100/120-Hz con-
version (display frequency doubling)
– two I
2
C-controlled PWM outputs
– beam current limiter
Fig. 1–1:
Block diagram of the DDP 3310B
Y Features
C Features
Digital
RGB
Matrix
DACs
Display
Frequency
Doubling
Hori-
zontal
Scaler
I
2
C
Inter-
face
3 x DAC
(10 Bit)
Tube Control
Analog
RGB
Switch
Picture
Frame
Generator
Measure-
ment
ADC
RGB
Out
2xRGB/FB
In
SDA/SCL
Sense
Input
HDrive
V & E/W
YC
r
C
b
4:2:2/4:1:1
2H / 2V
(1H/1V)
FIFO
Controlling
Clock
Gen.
Line-locked
Clock
27/32 MHz
PWM
PWM
1&2
SVM
Scan
Velocity
Modulation
H / V
Deflection
Security
Unit
HFlyback
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