DS3181/DS3182/DS3183/DS3184
76
Figure 8-26 shows a multidevice transmit-interface multiple cell transfer to different PHY devices. On clock edge 2,
the ATM device places address ‘00h’ on the address bus (which is mapped to Port 1). PHY device '1' (Port 1)
indicates to the ATM device that it has a complete cell to send by asserting RDXA[1]. On clock edge 4, the ATM
device selects PHY device '1'. On clock edge 5, the ATM device asserts
REN. On clock edge 6, the PHY device ‘1’
starts a cell transfer to the ATM device by placing the first byte of cell data on RDATA, and asserting RSOX to
indicate the transfer of the first byte of the cell. On clock edge 7, the PHY device deasserts RSOX as it continues to
place additional bytes of the cell on RDATA. On clock edge 13, PHY device ‘2’ asserts RDXA[2] to indicate to the
ATM device that it is ready to send a cell. On clock edge 15, PHY device '1’ indicates that it cannot transfer a
complete cell by deasserting RDXA[1]. On clock edge 16, the ATM device deselects PHY device '1' and selects
PHY device '2' by deasserting
REN and placing PHY device '2's address on RADR. On clock edge 17, the ATM
device asserts REN. On clock edge 18, PHY device ‘2’ (Port 2) starts the transfer of a cell to the ATM device by
placing the first byte of cell data on RDATA, and asserting RSOX to indicate the transfer of the first byte of the cell.
On clock edge 18, the PHY device deasserts RSOX as it continues to place additional bytes of the cell on RDATA.
Figure 8-26. UTOPIA Level 2 Receive Cell Transfer Direct Mode
RADR
1
REN
RDATA
RSOX
19
20
…
RSCLK
H3
P43
P44
P45
P46
P47
P48
P42
H1
H2
01h
00h
Transfer
Cell From:
PORT 1
H2
H3
PORT 2
H1
23
45
7
6
8
10
11
12
13
14
15
16
17
18
9
RDXA[1]
RDXA[2]
RDXA[3]
RDXA[4]
Figure 8-27 shows a multidevice transmit-interface multiple cell transfer to different PHY devices. On clock edge 2,
the ATM device polls PHY device 'N'. On clock edge 3, PHY device 'N' indicates to the ATM device that it can
accept cell data by asserting TPXA. On clock edge 4, the ATM device selects PHY device 'N'. On clock edge 5, the
ATM device starts a cell transfer to PHY device 'N' by asserting
TEN, placing the first byte of cell data on TDATA,
and asserting TSOX to indicate the transfer of the first byte of the cell. On clock edge 6, the ATM device deasserts
TSOX as it continues to place additional bytes of the cell on TDATA. On clock edge 6, the ATM device also polls
PHY device 'O'. On clock edge 7, PHY device 'O' indicates that it can accept the transfer of a complete cell. On
clock edge 14, the ATM device polls PHY device 'N'. On clock edge 15, PHY device 'N' indicates that it cannot
accept the transfer of a complete cell. On clock edge 16, the ATM device deselects PHY device 'N' and selects
PHY device 'O' by deasserting
TEN and placing PHY device 'O's address on TADR. On clock edge 17, the ATM
device starts the transfer of a cell to PHY device 'O' by asserting
TEN, placing the first byte of cell data on TDATA,
and asserting TSOX to indicate the transfer of the first byte of the cell. On clock edge 18, the ATM device
deasserts TSOX as it continues to place additional bytes of the cell on TDATA.