DS3181/DS3182/DS3183/DS3184
82
On clock edge 14, PHY port '3' places the last byte of the packet on RDATA, and asserts REOP to indicate that this
is the last transfer of the packet. On clock edge 15, PHY port '3' deasserts RVAL and REOP ending the packet
transfer process, as well as, deasserting RDXA to indicate that it does not have another block of packet data or an
end of packet ready for transfer. On clock edge 16, the POS device indicates to PHY port '4' that it is ready to
accept a block of packet data by placing its address on RADR and leaving
REN asserted. On clock edge 17, PHY
port '4' starts a packet transfer by leaving RVAL asserted, placing the first byte of the packet on RDATA, and
asserting RSOX to indicate that this is the first transfer of the packet. On clock edge 18, PHY port '4' deasserts
RSOX as it leaves RVAL asserted and continues to place additional bytes of the packet on RDATA.
Figure 8-35. POS-PHY Level 2 Receive Multiple Packet Transfer from Different PHY
Ports/Devices (direct status mode)
RCLK
RDXA[1]
RADR
RDXA[2]
RDXA[3]
RDXA[4]
1
19
20
23
4
5
7
6
8
10
11
12
13
14
15
16
17
18
9
RSOX
REOP
RERR
RDATA
Transfer
From PHY
RVAL
REN
P34
P1
P2
P41
…
P42
P35
'4'
1F
'3'
'1'
'2'
…
P19
P20
P2
P63
X
P64
P3
'1'
'2'
'3'
'4'
P4
P43
P1
Figure 8-36 shows a multidevice transmit interface in packet transfer mode multiple packet transfer to different PHY
ports. On clock edge 2, the POS device polls PHY port 'N'. On clock edge 3, PHY port 'N' indicates to the POS
device that it can accept a block of packet data by asserting TPXA. On clock edge 4, the POS device selects PHY
port 'N'. On clock edge 5, the POS device starts a packet transfer to PHY port 'N' by asserting
TEN, placing the first
byte of packet data on TDATA, and asserting TSOX to indicate the transfer of the first byte of the packet. On clock
edge 6, the POS device deasserts TSOX as it continues to place additional bytes of the packet on TDATA. And,
PHY port 'N' drives its TSPA output high. On clock edge 10, the POS device polls PHY port 'M'. On clock edge 11,
the POS device asserts TEOP to indicate the transfer of the last byte of the packet to PHY port 'N' and PHY port
'M' indicates to the POS device that it can accept a block of packet data by asserting TPXA. On clock edge 12, the
POS device deasserts
TEN to end the packet transfer process to PHY port 'N' and selects PHY port 'M'. On clock
edge 13, the POS device starts a packet transfer to PHY port 'M' by asserting
TEN, placing the first byte of packet
data on TDATA, and asserting TSOX to indicate the transfer of the first byte of the packet. And, PHY port 'N' tri-
states its TSPA output. On clock edge 14, the POS device deasserts TSOX as it continues to place additional
bytes of the packet on TDATA. And, PHY port 'M' drives its TSPA output high.