參數(shù)資料
型號： DTMFDECODER-RD
廠商： Silicon Laboratories Inc
文件頁數(shù)： 108/178頁
文件大小： 0K
描述： KIT REF DESIGN DTMF DECODER
應用說明： DTMF Decoder Ref Design AppNote
標準包裝： 1
主要目的： 電信，DTMF 解碼器
嵌入式： 否
已用 IC / 零件： C8051F300
主要屬性： 8kHz 采樣速率模數(shù)轉換器
次要屬性： 16 個 Goertzel 濾波器
已供物品： 板，軟件
產品目錄頁面： 627 (CN2011-ZH PDF)
相關產品： 336-1535-5-ND - IC 8051 MCU 8K FLASH 14-SOIC
C8051F300-GMR-ND - IC 8051 MCU 8K FLASH 11QFN
336-1245-ND - IC 8051 MCU 8K FLASH 11QFN
其它名稱： 336-1283
Rev. 2.9
35
C8051F300/1/2/3/4/5
5.
ADC0 (8-Bit ADC, C8051F300/2)
The ADC0 subsystem for the C8051F300/2 consists of two analog multiplexers (referred to collectively as
AMUX0) with 11 total input selections, a differential programmable gain amplifier (PGA), and a 500 ksps, 8-
bit successive-approximation-register ADC with integrated track-and-hold and programmable window
detector (see block diagram in Figure 5.1). The AMUX0, PGA, data conversion modes, and window detec-
tor are all configurable under software control via the Special Function Registers shown in Figure 5.1.
ADC0 operates in both Single-ended and Differential modes, and may be configured to measure any Port
pin, the Temperature Sensor output, or VDD with respect to any Port pin or GND. The ADC0 subsystem is
enabled only when the AD0EN bit in the ADC0 Control register (ADC0CN) is set to logic 1. The ADC0 sub-
system is in low power shutdown when this bit is logic 0.
AMUX0
+
-
X
VDD
ADC0CF
AM
P0G
N
0
AM
P0G
N
1
AD
0SC0
AD
0SC1
AD
0SC2
AD
0SC3
AD
0SC4
8-Bit
SAR
ADC
RE
F
8
S
YSC
LK
AD
C
0
16
ADC0CN
AD
0CM
0
AD
0CM
1
AD
0CM
2
AD0
WI
N
T
AD0B
USY
AD0I
NT
AD0
T
M
AD
0EN
Timer 0 Overflow
Timer 2 Overflow
Timer 1 Overflow
Start
Conversion
000
AD0BUSY (W)
VDD
ADC0GT
ADC0LT
9-to-1
AMUX
AD0WINT
Temp
Sensor
10-to-1
AMUX
VDD
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
GND
001
010
011
1xx
CNVSTR Input
Comb.
Logic
AMX0SL
AM
X0
P
0
AM
X0
P
1
AM
X0
P
2
AM
X
0
N
3
AM
X
0
N
2
AM
X
0
N
1
AM
X
0
N
0
AM
X0
P
3
Figure 5.1. ADC0 Functional Block Diagram
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