參數(shù)資料
型號: DTMFDECODER-RD
廠商: Silicon Laboratories Inc
文件頁數(shù): 109/178頁
文件大?。?/td> 0K
描述: KIT REF DESIGN DTMF DECODER
應用說明: DTMF Decoder Ref Design AppNote
標準包裝: 1
主要目的: 電信,DTMF 解碼器
嵌入式:
已用 IC / 零件: C8051F300
主要屬性: 8kHz 采樣速率模數(shù)轉換器
次要屬性: 16 個 Goertzel 濾波器
已供物品: 板,軟件
產(chǎn)品目錄頁面: 627 (CN2011-ZH PDF)
相關產(chǎn)品: 336-1535-5-ND - IC 8051 MCU 8K FLASH 14-SOIC
C8051F300-GMR-ND - IC 8051 MCU 8K FLASH 11QFN
336-1245-ND - IC 8051 MCU 8K FLASH 11QFN
其它名稱: 336-1283
C8051F300/1/2/3/4/5
36
Rev. 2.9
5.1.
Analog Multiplexer and PGA
The analog multiplexers (AMUX0) select the positive and negative inputs to the PGA, allowing any Port pin
to be measured relative to any other Port pin or GND. Additionally, the on-chip temperature sensor or the
positive power supply (VDD) may be selected as the positive PGA input. When GND is selected as the
negative input, ADC0 operates in Single-ended Mode; all other times, ADC0 operates in Differential
Mode. The ADC0 input channels are selected in the AMX0SL register as described in SFR Definition 5.1.
The conversion code format differs in Single-ended versus Differential modes, as shown below. When in
Single-ended Mode (negative input is selected GND), conversion codes are represented as 8-bit unsigned
integers. Inputs are measured from ‘0’ to VREF x 255/256. Example codes are shown below.
Input Voltage
ADC0 Output (Conversion Code)
VREF x 255/256
0xFF
VREF x 128/256
0x80
VREF x 64/256
0x40
0
0x00
When in Differential Mode (negative input is not selected as GND), conversion codes are represented as
8-bit signed 2s complement numbers. Inputs are measured from –VREF to VREF x 127/128. Example
codes are shown below.
Input Voltage
ADC0 Output (Conversion Code)
VREF x 127/128
0x7F
VREF x 64/128
0x40
0
0x00
–VREF x 64/128
0xC0
–VREF
0x80
Important Note About ADC0 Input Configuration: Port pins selected as ADC0 inputs should be config-
ured as analog inputs and should be skipped by the Digital Crossbar. To configure a Port pin for analog
input, set to ‘0’ the corresponding bit in register P0MDIN. To force the Crossbar to skip a Port pin, set to ‘1’
the corresponding bit in register XBR0. See Section “12. Port Input/Output” on page 103 for more Port
I/O configuration details.
The PGA amplifies the AMUX0 output signal as defined by the AMP0GN1-0 bits in the ADC0 Configuration
register (SFR Definition 5.2). The PGA is software-programmable for gains of 0.5, 1, 2, or 4. The gain
defaults to 0.5 on reset.
5.2.
Temperature Sensor
The typical temperature sensor transfer function is shown in Figure 5.2. The output voltage (VTEMP) is the
positive PGA input when the temperature sensor is selected by bits AMX0P2-0 in register AMX0SL; this
voltage will be amplified by the PGA according to the user-programmed PGA settings.
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