參數(shù)資料
型號： DTMFDECODER-RD
廠商： Silicon Laboratories Inc
文件頁數(shù)： 76/178頁
文件大?。?/td> 0K
描述： KIT REF DESIGN DTMF DECODER
應用說明： DTMF Decoder Ref Design AppNote
標準包裝： 1
主要目的： 電信，DTMF 解碼器
嵌入式： 否
已用 IC / 零件： C8051F300
主要屬性： 8kHz 采樣速率模數(shù)轉(zhuǎn)換器
次要屬性： 16 個 Goertzel 濾波器
已供物品： 板，軟件
產(chǎn)品目錄頁面： 627 (CN2011-ZH PDF)
相關產(chǎn)品： 336-1535-5-ND - IC 8051 MCU 8K FLASH 14-SOIC
C8051F300-GMR-ND - IC 8051 MCU 8K FLASH 11QFN
336-1245-ND - IC 8051 MCU 8K FLASH 11QFN
其它名稱： 336-1283
Rev. 2.9
167
C8051F300/1/2/3/4/5
16.4. Register Descriptions for PCA
Following are detailed descriptions of the special function registers related to the operation of the PCA.
SFR Definition 16.1. PCA0CN: PCA Control
Bit7:
CF: PCA Counter/Timer Overflow Flag.
Set by hardware when the PCA Counter/Timer overflows from 0xFFFF to 0x0000. When the
Counter/Timer Overflow (CF) interrupt is enabled, setting this bit causes the CPU to vector
to the PCA interrupt service routine. This bit is not automatically cleared by hardware and
must be cleared by software.
Bit6:
CR: PCA Counter/Timer Run Control.
This bit enables/disables the PCA Counter/Timer.
0: PCA Counter/Timer disabled.
1: PCA Counter/Timer enabled.
Bits5–3: UNUSED. Read = 000b, Write = don't care.
Bit2:
CCF2: PCA Module 2 Capture/Compare Flag.
This bit is set by hardware when a match or capture occurs. When the CCF2 interrupt is
enabled, setting this bit causes the CPU to vector to the PCA interrupt service routine. This
bit is not automatically cleared by hardware and must be cleared by software.
Bit1:
CCF1: PCA Module 1 Capture/Compare Flag.
This bit is set by hardware when a match or capture occurs. When the CCF1 interrupt is
enabled, setting this bit causes the CPU to vector to the PCA interrupt service routine. This
bit is not automatically cleared by hardware and must be cleared by software.
Bit0:
CCF0: PCA Module 0 Capture/Compare Flag.
This bit is set by hardware when a match or capture occurs. When the CCF0 interrupt is
enabled, setting this bit causes the CPU to vector to the PCA interrupt service routine. This
bit is not automatically cleared by hardware and must be cleared by software.
R/W
Reset Value
CF
CR
—
CCF2
CCF1
CCF0
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
(bit addressable)
0xD8
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