參數(shù)資料
型號(hào): DTMFDECODER-RD
廠商: Silicon Laboratories Inc
文件頁(yè)數(shù): 94/178頁(yè)
文件大?。?/td> 0K
描述: KIT REF DESIGN DTMF DECODER
應(yīng)用說(shuō)明: DTMF Decoder Ref Design AppNote
標(biāo)準(zhǔn)包裝: 1
主要目的: 電信,DTMF 解碼器
嵌入式:
已用 IC / 零件: C8051F300
主要屬性: 8kHz 采樣速率模數(shù)轉(zhuǎn)換器
次要屬性: 16 個(gè) Goertzel 濾波器
已供物品: 板,軟件
產(chǎn)品目錄頁(yè)面: 627 (CN2011-ZH PDF)
相關(guān)產(chǎn)品: 336-1535-5-ND - IC 8051 MCU 8K FLASH 14-SOIC
C8051F300-GMR-ND - IC 8051 MCU 8K FLASH 11QFN
336-1245-ND - IC 8051 MCU 8K FLASH 11QFN
其它名稱: 336-1283
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C8051F300/1/2/3/4/5
22
Rev. 2.9
1.7.
8-Bit Analog to Digital Converter (C8051F300/2 Only)
The C8051F300/2 includes an on-chip 8-bit SAR ADC with a 10-channel differential input multiplexer and
programmable gain amplifier. With a maximum throughput of 500 ksps, the ADC offers true 8-bit accuracy
with an INL of ±1LSB. The ADC system includes a configurable analog multiplexer that selects both posi-
tive and negative ADC inputs. Each Port pin is available as an ADC input; additionally, the on-chip Temper-
ature Sensor output and the power supply voltage (VDD) are available as ADC inputs. User firmware may
shut down the ADC to save power.
The integrated programmable gain amplifier (PGA) amplifies the ADC input by 0.5, 1, 2, or 4 as defined by
user software. The gain stage is especially useful when different ADC input channels have widely varied
input voltage signals, or when it is necessary to "zoom in" on a signal with a large DC offset.
Conversions can be started in five ways: a software command, an overflow of Timer 0, 1, or 2, or an exter-
nal convert start signal. This flexibility allows the start of conversion to be triggered by software events, a
periodic signal (timer overflows), or external HW signals. Conversion completions are indicated by a status
bit and an interrupt (if enabled). The resulting 8-bit data word is latched into an SFR upon completion of a
conversion.
Window compare registers for the ADC data can be configured to interrupt the controller when ADC data is
either within or outside of a specified range. The ADC can monitor a key voltage continuously in back-
ground mode, but not interrupt the controller unless the converted data is within/outside the specified
range.
Figure 1.10. 8-Bit ADC Block Diagram
X
VDD
8
9-to-1
AMUX
Temp
Sensor
10-to-1
AMUX
VDD
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
DGND
Programmable Gain
Amplifier
Start
Conversion
Window Compare
Logic
Window
Compare
Interrupt
+
-
Configuration, Control, and Data Registers
Analog Multiplexer
T0 Overflow
TMR2 Overflow
T1 Overflow
Software Write
External
Convert Start
8-Bit
SAR
ADC
End of
Conversion
Interrupt
ADC Data
Register
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