參數(shù)資料
型號： DTMFDECODER-RD
廠商： Silicon Laboratories Inc
文件頁數(shù)： 41/178頁
文件大?。?/td> 0K
描述： KIT REF DESIGN DTMF DECODER
應用說明： DTMF Decoder Ref Design AppNote
標準包裝： 1
主要目的： 電信，DTMF 解碼器
嵌入式： 否
已用 IC / 零件： C8051F300
主要屬性： 8kHz 采樣速率模數(shù)轉(zhuǎn)換器
次要屬性： 16 個 Goertzel 濾波器
已供物品： 板，軟件
產(chǎn)品目錄頁面： 627 (CN2011-ZH PDF)
相關產(chǎn)品： 336-1535-5-ND - IC 8051 MCU 8K FLASH 14-SOIC
C8051F300-GMR-ND - IC 8051 MCU 8K FLASH 11QFN
336-1245-ND - IC 8051 MCU 8K FLASH 11QFN
其它名稱： 336-1283
Rev. 2.9
135
C8051F300/1/2/3/4/5
14.3. Multiprocessor Communications
9-Bit UART mode supports multiprocessor communication between a master processor and one or more
slave processors by special use of the ninth data bit. When a master processor wants to transmit to one or
more slaves, it first sends an address byte to select the target(s). An address byte differs from a data byte
in that its ninth bit is logic 1; in a data byte, the ninth bit is always set to logic 0.
Setting the MCE0 bit (SCON.5) of a slave processor configures its UART such that when a stop bit is
received, the UART will generate an interrupt only if the ninth bit is logic one (RB80 = 1) signifying an
address byte has been received. In the UART interrupt handler, software will compare the received
address with the slave's own assigned 8-bit address. If the addresses match, the slave will clear its MCE0
bit to enable interrupts on the reception of the following data byte(s). Slaves that weren't addressed leave
their MCE0 bits set and do not generate interrupts on the reception of the following data bytes, thereby
ignoring the data. Once the entire message is received, the addressed slave resets its MCE0 bit to ignore
all transmissions until it receives the next address byte.
Multiple addresses can be assigned to a single slave and/or a single address can be assigned to multiple
slaves, thereby enabling "broadcast" transmissions to more than one slave simultaneously. The master
processor can be configured to receive all transmissions or a protocol can be implemented such that the
master/slave role is temporarily reversed to enable half-duplex transmission between the original master
and slave(s).
Master
Device
Slave
Device
TX
RX
TX
Slave
Device
RX
TX
Slave
Device
RX
TX
+5V
Figure 14.6. UART Multi-Processor Mode Interconnect Diagram
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DTMH04-2PB 制造商:TE Connectivity / Deutsch 功能描述:RECEPTACLE DTM HI TEMP B KEY 2WAY 制造商:TE Connectivity / Deutsch 功能描述:RECEPTACLE, DTM HI TEMP, B KEY, 2WAY 制造商:TE Connectivity / Deutsch 功能描述:RECEPTACLE, DTM HI TEMP, B KEY, 2WAY; Series:DTMH; Gender:Receptacle; No. of Contacts:2; No. of Rows:1; Contact Gender:Pin; Connector Mounting:Cable; Connector Shell Size:-; Contact Termination:Crimp; Contact Material:Copper; Contact;RoHS Compliant: Yes
DTMH04-2PC 制造商:TE Connectivity / Deutsch 功能描述:RECEPTACLE DTM HI TEMP C KEY 2WAY 制造商:TE Connectivity / Deutsch 功能描述:RECEPTACLE, DTM HI TEMP, C KEY, 2WAY 制造商:TE Connectivity / Deutsch 功能描述:RECEPTACLE, DTM HI TEMP, C KEY, 2WAY; Series:DTMH; Gender:Receptacle; No. of Contacts:2; No. of Rows:1; Contact Gender:Pin; Connector Mounting:Cable; Connector Shell Size:-; Contact Termination:Crimp; Contact Material:Copper; Contact;RoHS Compliant: Yes
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