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參數(shù)資料
| 型號： | GT-48002A |
| 廠商： | Galileo Technology Services, LLC |
| 英文描述： | Switched Fast Ethernet Controller for 100BaseX(100BaseX交換式快速以太網(wǎng)控制器) |
| 中文描述： | 交換式快速以太網(wǎng)控制器（100BaseX交換式快速以太網(wǎng)控制器的100BaseX） |
| 文件頁數(shù)： | 45/102頁 |
| 文件大小： | 1001K |
| 代理商： | GT-48002A |
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Switched Fast Ethernet Controller
Revision 1.2
47
All ports are fully loaded
All packets must be routed across the PCI bus (not switched between ports in the same device.)
11.4
Plug-and-Play Considerations In PCI Systems
In “Plug-and-Play” systems, the BIOS writes 0xFFFF.FFFF to the DRAM Base Address Register (0x10) and reads back
the results to determine how much PCI memory space the device requires. If there are multiple GalNet devices in a
system, 128Mbytes of PCI Memory Space can be allocated by a single device with the use of the ConfigMode pin.
When ConfigMode is LOW, The GT-48002A requests 4 MBytes of PCI address space. When the DRAM Base Address
register is read back, it will report 0xFFC0.0000 (bits [21:0] are ‘0’). When ConfigMode is HIGH, the GT-48002A
requests 128 MBytes of PCI address space. When the DRAM Base Address register is read back, it will report
0xF800.0000 (bits [27:0] are ‘0’).
Please note that only one GT-48002A should request 128Mbytes of PCI memory address space. In other words, only
one device should have ConfigMode tied HIGH. The remaining GalNet devices should only request 4Mbytes of
address space (ConfigMode tied LOW). Once the BIOS has completed memory space allocation, the GalNet devices
which were only allocated 4Mbytes of memory address space should be re-mapped into the single 128Mbyte GalNet
Protocol Region allocated by the GT-48002A which requested this space.
11.5
Unused PCI Bus in Stand-Alone Systems
Single-chip stand-alone applications do not require use of the PCI bus. The PCI bus pins must be connected as shown
in Table 24 to insure proper operation when not using the PCI bus. All pull-up and pull-down resistors should have a
value of 4.7K
. Be sure to have your own reset and 33.0 MHz clock on-board. All other PCI bus signals can remain
unconnected.
11.6
PCI Bus Arbiter in Multiple GalNet Device Systems
All GalNet systems that use more than one device will require a PCI bus arbiter. The arbiter examines the bus request
signals from each device and determines which device is granted the bus. Galileo provides reference designs for PCI
bus arbiters (implemented in inexpensive PALs) on our website.
It is important to note that individual systems may have different arbiter design requirements. For example, if your sys-
tem has several GT-48001A devices and a single GT-48002A (100-Mbps switch) it may make sense to give higher pri-
ority to the higher-speed 100BaseX interfaces.
Table 24: Pin Strapping Requirements for Unused PCI Signals
Pi n Na m e
St ra ppi ng
DevSel*
Pulled up to Vcc
Stop*
Pulled up to Vcc
Par*
No Connect
PErr*
Pulled up to Vcc
Frame*
Pulled up to Vcc
IRdy*
Pulled up to Vcc
TRdy*
Pulled up to Vcc
Gnt*
Pulled down to GND
IdSel*
Pulled down to GND
SErr*
No Connect
Req*
No Connect
Int*
No Connect
AD[31:0]
No Connect
CBE[3:0]
No Connect
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相關(guān)代理商/技術(shù)參數(shù) |
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| GT48300-A1-BBE1C083 | 制造商:Marvell 功能描述:Marvell GT48300-A1-BBE1C083 |
| GT48300-A1-BBE-C000 | 制造商:Marvell 功能描述:Marvell GT48300-A1-BBE-C000 |
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