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參數(shù)資料
| 型號： | GT-48002A |
| 廠商： | Galileo Technology Services, LLC |
| 英文描述： | Switched Fast Ethernet Controller for 100BaseX(100BaseX交換式快速以太網(wǎng)控制器) |
| 中文描述： | 交換式快速以太網(wǎng)控制器（100BaseX交換式快速以太網(wǎng)控制器的100BaseX） |
| 文件頁數(shù)： | 55/102頁 |
| 文件大?。?/td> | 1001K |
| 代理商： | GT-48002A |
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GT-48002A Switched Fast Ethernet Controller
56
Revision 1.2
Figure 11: GT-48002A MDIO Setup and Hold Time
Table 30: MDIO Signal Timings (PHY Driving MDIO)
13.2
Link Detection and Link Detection Bypass (ForceLinkPass*)
Typically, the GT-48002A will continuously query the PHY devices for its link status, without CPU intervention. The pre-
defined PHY addresses for the link query are 1 and 2 (out of possible 32 addresses). The GT-48002A will alternately
read register 1 from PHY1 and PHY2 and update the internal link bits according to the value of bit 2 of register 1. In the
case of “l(fā)ink is down” (i.e. bit 2 is ‘0’), that port will enter link test fail state. In this state, all of the port’s logic is reset. The
port will exit from link test fail state only when the “l(fā)ink is up” i.e. bit 2 of register 1 is read from the port’s PHY as ‘1’.
The GT-48002A offers the option to disable the link detection mechanism by forcing the link state of both ports to the
link test pass state. This is done with the ForceLinkPass* pin, which is sample at RESET. When ForceLinkPass* is
LOW on RESET, the link status of both ports remains in the “l(fā)ink is up” state regardless of the PHY’s link bit value.
When ForceLinkPass* is HIGH on RESET, the link status of the ports is read through the SMI from the PHY devices
(register 1, bit 2).
GT- 48002A
I E E E 80 2 . 3u S p ec .
Na m e
Pa ra m e te r
MI N
MAX
MI N
MAX
Un its
t5
Setup Time to Rising MDC
10
ns
t6
Hold Time after Rising MDC
10
ns
t5
MDC
MDIO
t6
Vih
min
Vil
max
Vih
min
Vil
max
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