參數(shù)資料
型號(hào)： GT-48002A
廠商： Galileo Technology Services, LLC
英文描述： Switched Fast Ethernet Controller for 100BaseX(100BaseX交換式快速以太網(wǎng)控制器)
中文描述： 交換式快速以太網(wǎng)控制器（100BaseX交換式快速以太網(wǎng)控制器的100BaseX）
文件頁(yè)數(shù)： 53/102頁(yè)
文件大?。?/td> 1001K
代理商： GT-48002A
GT-48002A Switched Fast Ethernet Controller
54
Revision 1.2
13.
MII Management Interface (SMI)
The GT-48002A MAC contains an MII Management Interface (SMI) for an MII compliant PHY devices. This allows con-
trol and status parameters to be passed between the GT-48002A and the PHY (parameters specified by the CPU) by
one serial pin (MDIO) and a clocking pin (MDC), reducing the number of control pins required for PHY mode control.
Typically, the GT-48002A will continuously query the PHY devices for their link status, without CPU intervention. The
predefined PHY addresses for the link query are 1 and 2 (out of possible 32 addresses). This protocol complies with
the National DP83840 PHY device as well as other available PHYs.
A CPU connected to the GT-48002A has access to all of the PHY addresses/registers, by writing and reading to/from a
dedicated set of GT-48002A SMI control registers. The SMI allows the CPU to have direct control over an MII-compat-
ible PHY device via the GT-48002A SMI control register. This allows the driver software to place the PHY in specific
modes such as Full Duplex, Loopback, Power Down, 10/100 speed selection as well as control of the PHY device’s
Auto-Negotiation function, if it exists. The CPU writes commands to the GT-48002A SMI register and the GT-48002A
reads or writes control/status parameters to the PHY device via a serial, bi-directional data pin called MDIO. These
serial data transfers are clocked by the GT-48002A MDC clock output.
13.1
SMI Cycles
The SMI protocol consists of a bit stream that is driven or sampled by the GT-48002A on each rising edge of the MDC
clock. The bit stream format of the SMI frame is described in Table 27.
PRE (Preamble). At the beginning of each transaction, the GT-48002A sends a sequence of 32 contiguous
logic one bits on MDIO with 32 corresponding cycles on MDC to provide the PHY with a pattern that it can use
to establish synchronization.
ST (Start of Frame). A Start of Frame pattern of 01.
OP (Operation Code). 10 - Read; 01 - Write
PhyAd (PHY Address). A 5 bit address of the PHY device (32 possible addresses). The first PHY address bit
transmitted by the GT-48002A is the MSB of the address.
RegAd (Register Address). A 5 bit address of the PHY register (32 possible registers in each PHY). The first
register address bit transmitted by the GT-48002A is the MSB of the address. The GT-48002A always queries
the PHY device for status of the link by reading register 1, bit 2.
TA (Turn Around). The turnaround time is a 2 bit time spacing between the Register Address field and the Data
field of the SMI frame to avoid contention during a read transaction. During a Read transaction the PHY should
not drive MDIO in the first bit time and drive ‘0’ in the second bit time. During a write transaction, the GT-
48002A drives a ‘10’ pattern to fill the TA time.
Data (Data). The data field is 16 bits long. The PHY drives the data field during Read transactions. The GT-
48002A drives the data field during write transactions. The first data bit transmitted and received shall be bit 15
of the PHY register being addressed.
IDLE (Idle). The IDLE condition on MDIO is a high impedance state. The MDIO driver is disabled and the PHY
should pull-up the MDIO line to a logic one.
13.1.1 SMI Timing Requirements
Figure 9 shows a waveform of the MDC line which is driven by the GT-48002A. Table 28 shows typical MDC timings.
Table 27: SMI Bit Stream Format
PRE
ST
OP
Ph y A d
Re g Ad
TA
Da t a
ID LE
READ
1...1
01
10
AAAAA
RRRRR
Z0
D..D(16)
Z
WRITE
1...1
01
AAAAA
RRRRR
10
D..D(16)
Z
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