參數(shù)資料
型號： GT-48002A
廠商： Galileo Technology Services, LLC
英文描述： Switched Fast Ethernet Controller for 100BaseX(100BaseX交換式快速以太網(wǎng)控制器)
中文描述： 交換式快速以太網(wǎng)控制器（100BaseX交換式快速以太網(wǎng)控制器的100BaseX）
文件頁數(shù)： 56/102頁
文件大?。?/td> 1001K
代理商： GT-48002A
Switched Fast Ethernet Controller
Revision 1.2
57
14.
Network Management Support
The GT-48002A supports the following management features:
HP-EASE packet sampling technology
Repeater MIB and PCI counters
Station-to-Station connectivity matrix
Port monitoring (sniffer) mode
This section describes the MIB counter, connectivity matrix and port mirroring functions. The HP-EASE functions are
described in the following section.
14.1
Repeater MIB and PCI Counters
The GT-48002A incorporates a full set of Repeater MIB counters for each Ethernet port, as well as counters for activity
on the PCI interface. Counters are accessed by the management CPU through the PCI interface.
The Repeater MIB counters include the following:
Bytes Received
Bytes Sent
Frames Received
Frames Sent
Total Bytes Received (Good and Bad)
Total Frames Received (Good and Bad)
Multicast Frames Received
Broadcast Frames Received
CRC + Alignment Error
Oversize Frames
Fragments
Jabber Frames
Collision
Late Collision
Frames with length of 64 Bytes
Frames with length of between 65-127 Bytes
Frames with length of between 128-255 Bytes
Frames with length of between 256-511 Bytes
Frames with length of between 512-1023 Bytes
Frames with length of between 1024-1522 Bytes
MAC Receive Error (received packets with RxEr asserted)
Dropped Frames
The global PCI counters are:
PCI Frames Received
PCI Frames Sent
Please see the register description section below for more information on the repeater MIB registers.
14.2
Station-to-Station Connectivity Matrix
The GT-48002A provides a mechanism to record the Destination Port(s), Destination MAC Address, Source MAC
Address and the Byte Count of all the forwarding packets in an external FIFO for RMON Station-to-Station (STS) Con-
nectivity Matrix support. The FIFO is connected to the DRAM’s data lines and controlled directly by the GT-48002A.
The GT-48002A asserts the ChipSel* pin, and reads the packet routing, Byte count, the Destination Address and
Source Address. Figure 12 is a timing diagram which shows the relationship between the assertion of ChipSel*, DRAM
control signals and DRAM data lines for a one word burst read of RMON data. Figure 10 shows a multiple word burst
read of RMON data. An application note giving detailed information about hooking up a FIFO to the 48002A for station-
to-station connectivity support is located on Galileo’s website (http://www.galileoT.com).
相關PDF資料
PDF描述
GT-48004A Four Port Switched Fast Ethernet Controller(四端口、交換式快速以太網(wǎng)控制器)
GT-48006A Low Cost Two Port 10/100Mbps Ethernet Bridge/Switch Controller(低成本、雙端口10/100Mbps以太網(wǎng)橋式/交換式控制器)
GT-48207 Advanced Switched Ethernet Controllers for 10+10/100 BaseX(高級交換式 10+10/100 BaseX以太網(wǎng)控制器)
GT-48208 Advanced Switched Ethernet Controllers for 10+10/100 BaseX(高級交換式 10+10/100 BaseX以太網(wǎng)控制器)
GT-48212 Advanced Switched Ethernet Controllers for 10+10/100 BaseX(高級交換式 10+10/100 BaseX以太網(wǎng)控制器)
相關代理商/技術參數(shù)
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GT48212-A6-PBB1C000 制造商:Marvell 功能描述:
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GT48300-A1-BBE-C000 制造商:Marvell 功能描述:Marvell GT48300-A1-BBE-C000
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