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參數(shù)資料
| 型號： | GT-48002A |
| 廠商： | Galileo Technology Services, LLC |
| 英文描述： | Switched Fast Ethernet Controller for 100BaseX(100BaseX交換式快速以太網(wǎng)控制器) |
| 中文描述： | 交換式快速以太網(wǎng)控制器（100BaseX交換式快速以太網(wǎng)控制器的100BaseX） |
| 文件頁數(shù)： | 72/102頁 |
| 文件大小： | 1001K |
| 代理商： | GT-48002A |
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Switched Fast Ethernet Controller
Revision 1.2
71
18.
Interrupts
The GT-48002A signals interrupts to a management CPU via the PCI INTA# pin. Interrupts are maskable through the
Interrupt Mask register and the interrupt source is determined through the Interrupt Cause register. The Interrupt Mask
register defaults to masking all interrupts. A ‘0’ in the appropriate bit means that particular interrupt will be masked. A
‘1’ in the appropriate bit means that particular interrupt will not be masked. The default is that all interrupts are masked.
Interrupts are cleared by writing ‘0’ to the corresponding bit in the Interrupt Cause register. Writing ‘1’ to a bit in the
Cause register has no effect.
19.
RESET Configuration
The GT-48002A uses several pins as configuration inputs to set certain parameters following a RESET. The definition
of the configuration pins changes immediately after RESET to their usual function.
19.1
Configuration Pins
Configuration pins must be pulled up or down externally at RESET to select the desired operational parameter. The
recommended value of the pull-up/down resistors is 4.7K ohms. Table 34 shows the configuration pins for the GT-
48002A.
19.2
Configuration Input Timings
The configuration inputs have two timing requirements:
setup/hold time to clock (as any synchronous input)
setup of at least 10 clock cycles before RESET de-assertion (rising edge).
You can guarantee these parameters by using resistors to strap the configuration pins and delaying RESET de-asser-
tion until least 10 clock cycles after the clock is stable.
Table 34: RESET Pin Strapping Options
Pin
Co nf igu rat ion Fu nct i on
DAddr[4:0]
Device Number
DAddr[5]
DRAM Size
0-
1-
2Mbyte
1Mbyte
DAddr[6]
Half/Full Duplex Mode for Port 0
0-
1-
Half Duplex
Full Duplex
DAddr[7]
Half/Full Duplex Mode for Port 1
0-
1-
Half Duplex
Full Duplex
DAddr[8]
DRAM Type
0-
1-
Reserved
EDO
LEDMode*
LED Mode
0-
1-
LEDMode 0
LEDMode 1
ForceLinkPass*
Force Link Pass (For Both Port 0 and Port 1)
0-
1-
Force Link Status to “l(fā)ink is up”
Read Link Status from the PHY via SMI
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