參數(shù)資料
型號： GT-48002A
廠商： Galileo Technology Services, LLC
英文描述： Switched Fast Ethernet Controller for 100BaseX(100BaseX交換式快速以太網(wǎng)控制器)
中文描述： 交換式快速以太網(wǎng)控制器（100BaseX交換式快速以太網(wǎng)控制器的100BaseX）
文件頁數(shù)： 50/102頁
文件大?。?/td> 1001K
代理商： GT-48002A
Switched Fast Ethernet Controller
Revision 1.2
51
Figure 7: MII Transmit Signal Timing
Table 25: MII Signal Timings Sychronous to TxClk
12.8
10/100 Mbps MII Reception
Frame reception starts with the assertion of RxDV (while the GT-48002A is not transmitting) by the PHY. Once RxDV is
asserted, the GT-48002A will begin sampling incoming data on pins RxDV[3:0] on the rising edge of RxClk. Reception
ends when the RxDV is deasserted by the PHY. The last nibble sampled by the GT-48002A is the nibble present on
RxD[3:0] on the last RxClk rising edge in which RxDV is still asserted. During reception, the RxDV is asserted. If, while
RxDV is asserted, the GT-48002A detects the assertion of RxEr, it will designate this packet as corrupted. While no
reception is taking place, RxDV should remain deasserted.
A waveform of the signals which are synchronous to RxClk (RxD0[3:0], RxD1[3:0], RxDV[1:0], RxEr[1:0]) is shown in
Figure 8. The setup and hold times of the GT-48002A are tighter than the IEEE 802.3u standard, clause 22.3.2, as
shown in Table 26.
Figure 8: MII Receive Signal Timing
Table 26: MII Signal Timings Sychronous to RxClk
GT- 48002A
IE EE 802.3 u Spe c .
Na m e
Pa ra m e te r
MI N
MA X
MIN
MAX
Un its
vd
Valid Delay after Rising TxClk
2
14
0
25
ns
GT- 48002A
IE EE 802.3 u Spe c .
Na m e
Pa ra m e te r
MI N
MA X
MIN
MAX
Un its
ts
Setup Time to Rising RxClk
6
10
ns
th
Hold Time after Rising RxClk
1
10
ns
vd
TxClk
TxD, TxEn
Vih
min
Vil
max
Vih
min
Vil
max
ts
RxClk
RxD, RxDV,
RxEr
th
Vih
min
Vil
max
Vih
min
Vil
max
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