參數(shù)資料
型號(hào)： GT-48002A
廠商： Galileo Technology Services, LLC
英文描述： Switched Fast Ethernet Controller for 100BaseX(100BaseX交換式快速以太網(wǎng)控制器)
中文描述： 交換式快速以太網(wǎng)控制器（100BaseX交換式快速以太網(wǎng)控制器的100BaseX）
文件頁數(shù)： 90/102頁
文件大?。?/td> 1001K
代理商： GT-48002A
GT-48002A Switched Fast Ethernet Controller
88
Revision 1.2
22.4
PCI Global Counters, Offset: 0x140040 - 0x140044
The CPU must read all counters during initialization in order to reset the counters to ‘0’. All counters are 32-bits.
22.5
SMI Register, Offset: 0x14004c
22.6
PCI Configuration Registers
The GT- 48001 contains the required PCI configuration registers. These registers are accessed from the PCI.
Device and Vendor ID, PCI Offset: 0x000 (Read Only)
Table 37: PCI MIB Counters
Addr ess
C o u n t e r Na m e
Fun cti o n
In iti a l Va l u e
0x140040
PCIFraRec
Good Frames Received from the PCI
-
0x140044
PCIFraSent
Good Frames Sent to the PCI
-
Bi ts
Fi e l d Na m e
Fun cti o n
In iti a l Va l u e
15:0
Data
For SMI READ operation: Two PCI transactions are
required: (1) PCI write to the SMI register with
OpCode = 1, PhyAd, RegAd with the Data being any
value. (2) PCI read from the SMI register. When read-
ing back the SMI register, the Data is the addressed
Phy register contents if the ReadValid bit (#27) is 1.
The Data remains undefined as long as ReadValid is
0. No PCI write to the SMI register should take place
until the ReadValid is returned with the value of ‘1’.
For SMI WRITE operation: One PCI transaction is
required: PCI write to the SMI register with OpCode =
0, PhyAd, RegAd with the Data to be written to the
addressed Phy register. No PCI write to the SMI regis-
ter should take place until a minimum of 320 MDC
clock cycles have passed.
N/A
20:16
PhyAd
PHY device address
0x0
25:21
RegAd
PHY device register address
0x0
26
OpCode
0 - Write
1 - Read
0x1
27
ReadValid
1 - Indicates that the Read operation has been com-
pleted for the addressed RegAd register, and the data
is valid on the Data field. Once set, this bit is cleared
following the PCI read operation.
0x0
31:28
N/A
This bits should be driven 0x0 during any write to the
SMI register.
0x0
Bi ts
Fi e l d Na m e
Fun cti o n
In iti a l Va l u e
15:0
VenId
Vendor ID. Provides the manufacturer of the PCI
device. For the GT-48002A this is Galileo’s PCI ven-
dor ID (0x11ab.)
0x11ab
31:16
DevId
Provides the unique GT- 48002A device ID number
0x4802
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