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參數(shù)資料
| 型號： | GT-48002A |
| 廠商： | Galileo Technology Services, LLC |
| 英文描述： | Switched Fast Ethernet Controller for 100BaseX(100BaseX交換式快速以太網控制器) |
| 中文描述： | 交換式快速以太網控制器（100BaseX交換式快速以太網控制器的100BaseX） |
| 文件頁數(shù)： | 59/102頁 |
| 文件大小： | 1001K |
| 代理商： | GT-48002A |
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GT-48002A Switched Fast Ethernet Controller
6
Revision 1.2
1.
Functional Overview
The GT-48002A is a high-performance, low-cost, Switched Fast Ethernet Controller that provides packet switching
functions between two, on-chip, 10/100Mbps, auto-negotiated ports and the 1Gbps PCI backplane. The GT-48002A
uses the innovative GalNet Switching Architecture to allow expansion to additional Ethernet, Fast Ethernet and 100VG-
AnyLAN ports. The GT-48002A is backwards compatible with the GT-48002.
1.1
The GalNet Switching Architecture
The GalNet Switching Architecture is based on a proprietary messaging protocol using the industry standard PCI bus
as a medium. GalNet devices are designed to connect seamlessly allowing packets to be switched between devices
without processor intervention (see Figure 1). Each GalNet device acts as an intelligent agent, sharing information
between all other devices in the system. For example, when one GalNet device learns a new address, it automatically
updates all other GalNet devices via the NEW_ADDRESS message. GalNet messages are defined as
write-only
(request/response) in order to achieve the maximum bandwidth from the PCI bus.
The GalNet Architecture Family currently consists of three products: the GT-48001A (eight ports of 10BaseX), the GT-
48002A (two ports of 100BaseX), and the GT-48003 (two ports of 100VG-AnyLAN). In addition, Galileo Technology
provides a number of other complementary PCI interface products for popular microprocessors.
1.2
Fast Ethernet Ports
The GT-48002A integrates two Fast Ethernet ports. Each port works at 10/100Mbps (half-duplex) or 20/200Mbps (full-
duplex). Two Media Independent Interfaces (MII) are provided for glueless connection to off-the-shelf PHY chips. The
GT-48002A supports full auto-negotation for capable PHYs. Therefore, the speed (10 or 100 Mbps) and duplex (half or
full) which the PHY resolves to operate is automatically reported to the GT-48002A in both managed and unmanaged
systems. The port can also be forced to operate in a certain mode, if so desired. Each port includes the Media Access
Control function (MAC) and six LEDs for Link Status, Collision, Receive Transmit, Half/Full Duplex and Receive Buffer
Full indications. The GT-48002A incorporates full MII management support. The MDC/MDIO pins are directly con-
trolled by the CPU.
Figure 1: Typical 16-port 10-Mbps plus 2-port 100-Mbps Unmanaged Switch Implementation
REQ/GNT PAIR
PCI BUS
GT-48001A
8-Port 10BaseX
Switch
8 10BaseX Ports
GT-48001A
8-Port 10BaseX
Switch
8 10BaseX Ports
GT-48002A
2-Port 100BaseX
Switch
2 100BaseX Ports
PCI BUS
ARBITER
REQ/GNT PAIR
NOTES:
1) Required PHY circuitry and magnetics not shown
2) PCI bus arbiter is typically implemented in a PAL
3) EDO DRAMs per device are not shown
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