![](http://datasheet.mmic.net.cn/110000/GT-48002A_datasheet_3491731/GT-48002A_49.png)
Switched Fast Ethernet Controller
Revision 1.2
49
and 2 alternately), implemented as READ commands issued via the MDC/MDIO interface:
1.
Read the PHY Auto-Negotiation Complete status. As long as PHY bit 1.5 (Register 1, bit 5) is '0' switch to Half-
Duplex mode and continue to read PHY register bit 1.5. Continue to step 2 when PHY bit 1.5 is '1', signaling Auto-
negotiation is complete.
Steps 2 through 6 are performed once for every transition of PHY bit 1.5 from '0' to '1'. Once PHY bit 1.5 remains '1'
and PHY registers 4 and 5 have already been read, the GT-48002A will continue to read PHY register 1, and monitor
PHY bit 1.5. Steps 2 to 6 are performed once, if after Rst* de-assertion, the PHY bit 1.5 is read as '1', in order to update
the GT-48002A duplex mode.
NOTE: PHY bit 1.2 (Link Status) is read and latched during this same register read operation, regardless of the Auto-
Negotiation status.
2.
Read the Auto-Negotiation Advertisement register, PHY Register 4. Continue to step 3.
3.
Read the Auto-Negotiation Link Partner Ability register, PHY Register 5. Continue to step 4.
4.
Resolve the highest common ability of the two link partners in the following manner (according to the 802.3u Prior-
ity Resolution clause 28B.3):
if (bit 4.8 AND bit 5.8) == '1' then ability is 100BASE-TX Full Duplex
else if (bit 4.9 AND bit 5.9) == '1' then ability is 100BASE-T4 Half Duplex
else if (bit 4.7 AND bit 5.7) == '1' then ability is 100BASE-TX Half Duplex
else if (bit 4.6 AND bit 5.6) == '1' then ability is 10BASE-T Full Duplex
else ability is 10BASE-T Half Duplex;
Continue to step 5.
5.
Resolve the duplex mode of the two link partners in the following manner:
if ( (ability == "100BASE-TX Full Duplex") or (ability == "10BASE-T Full Duplex") ) then
duplex mode = FULL DUPLEX
else duplex mode = HALF DUPLEX;
NOTE: the value of the duplex mode indication should change only after reading both PHY registers 4 and 5. Continue
to step 6.
6.
Update the Port Control Register by writing the correct duplex mode bit. Continue with step 1.
12.3.3 Auto-negotiation Control Per Port
Since EnAutoNeg* pin enables or disables auto-negotiation for both ports, applications which require one port to auto-
negotiate and one port to be forced into a certain mode require an additional PLD to interface between the GT-
48002A’s MDIO and MDC pin and the PHY.
While the GT-48002A waits for auto-negotiation to complete on a port, it forces that particular port to half-duplex mode.
If this port is not auto-negotiation capable (but supports full duplex mode), or the port needs to be forced to full-duplex
while the other is left to auto-negotiate, the PLD will monitor the MDIO line and make some modifications to the data
read by GT-48002A from the PHYs. Therefore, instead of defaulting to half-duplex, the modified data read back by the
GT-48002A will place the port in full-duplex. In essence, the PLD mimics the completion of the auto-negotiation cycle
with a device that is not capable to auto-negotiate. For detailed information about implementing auto-negotiation on a
per port basis, including the required PLD equations, please download the application note located on Galileo’s web-
site (http://www.galileoT.com).