參數(shù)資料
型號： ICS1893AFLFT
廠商： IDT, Integrated Device Technology Inc
文件頁數(shù)： 127/136頁
文件大?。?/td> 0K
描述： PHYCEIVER LOW PWR 3.3V 48-SSOP
標準包裝： 1,000
系列： PHYceiver™
類型： PHY 收發(fā)器
規(guī)程： MII
電源電壓： 3.14 V ~ 3.47 V
安裝類型： 表面貼裝
封裝/外殼： 48-BSSOP（0.295"，7.50mm 寬）
供應商設備封裝： 48-SSOP
包裝： 帶卷 (TR)
其它名稱： 1893AFLFT
ICS1893AF, Rev D 10/26/04
October, 2004
90
Chapter 8
Management Register Set
ICS1893AF Data Sheet - Release
Copyright 2004, Integrated Circuit Systems, Inc.
All rights reserved.
8.12.5
100Base PLL Lock Error (bit 17.9)
The Phase-Locked Loop (PLL) Lock Error bit indicates to an STA whether the ICS1893AF has ever
experienced a PLL Lock Error. A PLL Lock Error occurs when the PLL fails to lock onto the incoming
100Base data stream. If this bit is set to a logic:
Zero, it indicates that a PLL Lock Error has not occurred since either the last read or reset of this register.
One, it indicates that a PLL Lock Error has occurred since either the last read or reset of this register.
This bit is a latching high bit. (For more information on latching high and latching low bits, see Section
Note:
This bit has no definition in 10Base-T mode.
8.12.6
False Carrier (bit 17.8)
The False Carrier bit indicates to an STA the detection of a False Carrier by the ICS1893AF in 100Base
mode.
A False Carrier occurs when the ICS1893AF begins evaluating potential data on the incoming 100Base
data stream, only to learn that it was not a valid /J/K/. If this bit is set to a logic:
Zero, it indicates a False Carrier has not been detected since either the last read or reset of this register.
One, it indicates a False Carrier was detected since either the last read or reset of this register.
This bit is a latching high bit. (For more information on latching high and latching low bits, see Section
Note:
This bit has no definition in 10Base-T mode.
8.12.7
Invalid Symbol (bit 17.7)
The Invalid Symbol bit indicates to an STA the detection of an Invalid Symbol in a 100Base data stream by
the ICS1893AF.
When the ICS1893AF is receiving a packet, it examines each received Symbol to ensure the data is error
free. If an error occurs, the port indicates this condition to the MAC/repeater by asserting the RXER signal.
In addition, the ICS1893AF sets its Invalid Symbol bit to logic one. Therefore, if this bit is set to a logic:
Zero, it indicates an Invalid Symbol has not been detected since either the last read or reset of this
register.
One, it indicates an Invalid Symbol was detected since either the last read or reset of this register.
This bit is a latching high bit. (For more information on latching high and latching low bits, see Section
Note:
This bit has no definition in 10Base-T mode.
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相關代理商/技術參數(shù)
參數(shù)描述
ICS1893AFT 功能描述:PHYCEIVER LOW PWR 3.3V 48-SSOP RoHS:否 類別:集成電路 (IC) >> 接口 - 驅動器，接收器，收發(fā)器 系列:PHYceiver™ 標準包裝:1,000 系列:- 類型:收發(fā)器 驅動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.295"，7.50mm 寬） 供應商設備封裝:16-SOIC 包裝:帶卷 (TR)
ICS1893AG 制造商:ICS 制造商全稱:ICS 功能描述:3.3 V 10Base-T/100Base-TX Integrated PHYceiver-TM
ICS1893AGI 制造商:ICS 制造商全稱:ICS 功能描述:3.3 V 10Base-T/100Base-TX Integrated PHYceiver-TM
ICS1893AGILF 制造商:ICS 制造商全稱:ICS 功能描述:3.3 V 10Base-T/100Base-TX Integrated PHYceiver-TM
ICS1893AGLF 制造商:ICS 制造商全稱:ICS 功能描述:3.3 V 10Base-T/100Base-TX Integrated PHYceiver-TM
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