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參數(shù)資料
| 型號： | ICS1893AFLFT |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 95/136頁 |
| 文件大小： | 0K |
| 描述： | PHYCEIVER LOW PWR 3.3V 48-SSOP |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 系列： | PHYceiver™ |
| 類型： | PHY 收發(fā)器 |
| 規(guī)程： | MII |
| 電源電壓： | 3.14 V ~ 3.47 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-BSSOP（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 48-SSOP |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | 1893AFLFT |
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Chapter 8
Management Register Set
ICS1893AF, Rev. D 10/26/04
October, 2004
61
ICS1893AF Data Sheet - Release
Copyright 2004, Integrated Circuit Systems, Inc.
All rights reserved.
8.2.5
Low Power Mode (bit 0.11)
This bit provides one way to control the ICS1893AF low-power mode function. When bit 0.11 is logic:
Zero, there is no impact to ICS1893AF operations.
One, the ICS1893AF enters the low-power mode. In this case, the ICS1893AF disables all internal
functions and drives all MAC/repeater output pins low except for those that support the MII Serial
Management Port. In addition, the ICS1893AF internally activates the TPTRI function to tri-state the
signals on the Twisted-Pair Transmit pins (TP_TXP and TP_TXN) and achieve additional power savings.
Note:
There are two ways the ICS1893AF can enter low-power mode. When entering low-power mode:
By setting bit 0.11 to logic one, the ICS1893AF maintains the value of all Management Register
bits except the latching high (LH) and latching low (LL) status bits, which are re-initialized to their
default values instead. (For more information on latching high and latching low bits, see Section
During a reset, the ICS1893AF sets all management register bits to their default values.
8.2.6
Isolate (bit 0.10)
This bit controls the ICS1893AF Isolate function. When bit 0.10 is logic:
Zero, there is no impact to ICS1893AF operations.
One, the ICS1893AF electrically isolates its data paths from the MAC/Repeater Interface. The
ICS1893AF places all MAC/repeater output signals (TXCLK, RXCLK, RXDV, RXER, RXD[3:0], COL,
and CRS) in a high-impedance state and it isolates all MAC/repeater input signals (TXD[3:0], TXEN, and
TXER). In this mode, the Serial Management Interface continues to operate normally (that is, bit 0.10
does not affect the Management Interface).
The default value for bit 0.10 depends upon the PHY address of Table 8-16. If the PHY address:
Is equal to 00000b, then the default value of bit 0.10 is logic one, and the ICS1893AF isolates itself from
the MAC/Repeater Interface.
Is not equal to 00000b, then the default value of bit 0.10 is logic zero, and the ICS1893AF does not
isolate its MAC/Repeater Interface.
8.2.7
Restart Auto-Negotiation (bit 0.9)
This bit allows an STA to restart the auto-negotiation process in Software mode (that is, the HW/SW pin is
logic one). When bit 0.12 is logic:
Zero, the Auto-Negotiation sublayer is disabled, and the ICS1893AF isolates any attempt by the STA to
set bit 0.9 to logic one.
One (as set by an STA), the ICS1893AF restarts the auto-negotiation process. Once the auto-negotiation
process begins, the ICS1893AF automatically sets this bit to logic zero, thereby providing the
self-clearing feature.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICS1893AFT | 功能描述:PHYCEIVER LOW PWR 3.3V 48-SSOP RoHS:否 類別:集成電路 (IC) >> 接口 - 驅(qū)動器，接收器，收發(fā)器 系列:PHYceiver™ 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:收發(fā)器 驅(qū)動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC 包裝:帶卷 (TR) |
| ICS1893AG | 制造商:ICS 制造商全稱:ICS 功能描述:3.3 V 10Base-T/100Base-TX Integrated PHYceiver-TM |
| ICS1893AGI | 制造商:ICS 制造商全稱:ICS 功能描述:3.3 V 10Base-T/100Base-TX Integrated PHYceiver-TM |
| ICS1893AGILF | 制造商:ICS 制造商全稱:ICS 功能描述:3.3 V 10Base-T/100Base-TX Integrated PHYceiver-TM |
| ICS1893AGLF | 制造商:ICS 制造商全稱:ICS 功能描述:3.3 V 10Base-T/100Base-TX Integrated PHYceiver-TM |
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