參數(shù)資料
型號: ICS1893AFLFT
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 25/136頁
文件大?。?/td> 0K
描述: PHYCEIVER LOW PWR 3.3V 48-SSOP
標(biāo)準(zhǔn)包裝: 1,000
系列: PHYceiver™
類型: PHY 收發(fā)器
規(guī)程: MII
電源電壓: 3.14 V ~ 3.47 V
安裝類型: 表面貼裝
封裝/外殼: 48-BSSOP(0.295",7.50mm 寬)
供應(yīng)商設(shè)備封裝: 48-SSOP
包裝: 帶卷 (TR)
其它名稱: 1893AFLFT
ICS1893AF, Rev D 10/26/04
October, 2004
120
Chapter 10
DC and AC Operating Conditions
ICS1893AF Data Sheet - Release
Copyright 2004, Integrated Circuit Systems, Inc.
All rights reserved.
10.5.7
MII Management Interface Timing
Table 10-14 lists the significant time periods for the MII Management Interface timing (which consists of
timings of signals on the MDC and MDIO pins). Figure 10-8 shows the timing diagram for the time periods.
The ICS1893AF is tested at 25 MHz (a 40-ns period) with a 50-pF load. Designs must account for all board loading
of MDC.
Figure 10-8.
MII Management Interface Timing Diagram
Table 10-14.
MII Management Interface Timing
Time
Period
Parameter
Conditions
Min.
Typ.
Max.
Units
t1
MDC Minimum High Time
160
ns
t2
MDC Minimum Low Time
160
ns
t3
MDC Period
400
ns
t4
MDC Rise Time to MDIO Valid
0
300
ns
t5
MDIO Setup Time to MDC
10
ns
t6
MDIO Hold Time after MDC
10
ns
MDC
MDIO
(Output)
MDC
MDIO
(Input)
t1
t2
t3
t4
t5
t6
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