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參數(shù)資料
| 型號(hào)： | ICS1893AFLFT |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁(yè)數(shù)： | 86/136頁(yè) |
| 文件大小： | 0K |
| 描述： | PHYCEIVER LOW PWR 3.3V 48-SSOP |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 系列： | PHYceiver™ |
| 類型： | PHY 收發(fā)器 |
| 規(guī)程： | MII |
| 電源電壓： | 3.14 V ~ 3.47 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-BSSOP（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 48-SSOP |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | 1893AFLFT |
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Chapter 7
Functional Blocks
ICS1893AF, Rev. D 10/26/04
October, 2004
53
ICS1893AF Data Sheet - Release
Copyright 2004, Integrated Circuit Systems, Inc.
All rights reserved.
7.6.2.1
Management Frame Preamble
The ICS1893AF continually monitors its serial management interface for either valid data or a Management
Frame (MF) Preamble, based upon the setting of the MF Preamble Suppression bit, 1.6. When the MF
Preamble Suppression is disabled, an ICS1893AF waits for a MF Preamble which indicates the start of an
STA transaction. A Management Frame Preamble is a pattern of 32 contiguous logic one bits on the MDIO
pin, along with 32 corresponding clock cycles on the MDC pin.
The ICS1893AF supports the Management Frame (MF) Preamble Suppression capability on its
Management Interface, thereby providing a method to shorten the Management Frame and provide an STA
with faster access to the Management Registers.
The ability to process Management Frames that do not have a preamble is provided by the Management
Frame Preamble Suppression bit, (bit 1.6 in the ICS1893AF’s Status Register). This is an ISO/IEC defined
status bit that is intended to provide an indication of whether or not a PHY supports the MF Preamble
Suppression feature. In order to maintain backward compatibility with the ICS1890, which did not support
MF Preamble Suppression, the ICS1893AF MF Preamble Suppression bit is a Command Override Write
bit which defaults to a logic zero. An STA can enable MF Preamble Suppression by writing a logic one to bit
1.6 subsequent to a write of logic one to the Command Override bit, 16.15. For an explanation of the
Command Override Write bits, see Section 8.1.2, “Management Register Bit Access”.
7.6.2.2
Management Frame Start
A valid Management Frame includes a start-of-frame delimiter, SFD, immediately following the preamble.
The SFD bit pattern is 01b and is synchronous with two clock cycles on the MDC pin.
7.6.2.3
Management Frame Operation Code
A valid Management Frame includes an operation code (OP) immediately following the start-of-frame
delimiter. There are two valid operation codes: one for reading from a management register, 10b, and one
for writing to a management register, 01b. The ICS1893AF does not respond to the codes 00b and 11b,
which the ISO/IEC specification defines as invalid.
7.6.2.4
Management Frame PHY Address
The two-wire, Serial Management Interface is specified to allow busing (that is, the sharing of the two wires
among multiple PHYs). The Management Frame includes a 5-bit PHY Address field, PHYAD, allowing for
32 unique addresses. An STA uniquely identifies each of the PHYs that share a single serial management
interface by using this 5-bit PHY Address field, PHYAD.
Upon receiving a valid STA transaction, during a power-on or hardware reset an ICS1893AF compares the
PHYAD field included within the management frame with the value of its PHYAD bits stored in register 16.
(For information on the PHYAD bits, see Table 8-16.) An ICS1893AF responds to all transactions that
match its stored address bits.
7.6.2.5
Management Frame Register Address
A Management Frame includes a 5-bit register address field, REGAD. This field identifies which of the 32
Management Registers are involved in a transaction between an STA and a PHY.
7.6.2.6
Management Frame Operational Code
A management frame includes a 2-bit operational code field, OP. If the operation code is a:
Read, the REGAD field identifies the register used as the source of data returned to the STA by the
ICS1893AF.
Write, the REGAD identifies the destination register that is to receive the data sent by the STA to the
ICS1893AF.
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| ICS1893BFLFT | PHYCEIVER LOW PWR 3.3V 48-SSOP |
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相關(guān)代理商/技術(shù)參數(shù) |
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| ICS1893AFT | 功能描述:PHYCEIVER LOW PWR 3.3V 48-SSOP RoHS:否 類別:集成電路 (IC) >> 接口 - 驅(qū)動(dòng)器，接收器，收發(fā)器 系列:PHYceiver™ 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:收發(fā)器 驅(qū)動(dòng)器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC 包裝:帶卷 (TR) |
| ICS1893AG | 制造商:ICS 制造商全稱:ICS 功能描述:3.3 V 10Base-T/100Base-TX Integrated PHYceiver-TM |
| ICS1893AGI | 制造商:ICS 制造商全稱:ICS 功能描述:3.3 V 10Base-T/100Base-TX Integrated PHYceiver-TM |
| ICS1893AGILF | 制造商:ICS 制造商全稱:ICS 功能描述:3.3 V 10Base-T/100Base-TX Integrated PHYceiver-TM |
| ICS1893AGLF | 制造商:ICS 制造商全稱:ICS 功能描述:3.3 V 10Base-T/100Base-TX Integrated PHYceiver-TM |
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