參數(shù)資料
型號： ICS1893AFLFT
廠商： IDT, Integrated Device Technology Inc
文件頁數(shù)： 9/136頁
文件大小： 0K
描述： PHYCEIVER LOW PWR 3.3V 48-SSOP
標(biāo)準(zhǔn)包裝： 1,000
系列： PHYceiver™
類型： PHY 收發(fā)器
規(guī)程： MII
電源電壓： 3.14 V ~ 3.47 V
安裝類型： 表面貼裝
封裝/外殼： 48-BSSOP（0.295"，7.50mm 寬）
供應(yīng)商設(shè)備封裝： 48-SSOP
包裝： 帶卷 (TR)
其它名稱： 1893AFLFT
ICS1893AF, Rev D 10/26/04
October, 2004
106
Chapter 9
Pin Diagram, Listings, and Descriptions
ICS1893AF Data Sheet - Release
Copyright 2004, Integrated Circuit Systems, Inc.
All rights reserved.
MDIO
26
Input/
Output
Management Data Input/Output.
The signal on this pin can be tri-stated and can be driven by one of the
following:
A Station Management Entity (STA), to transfer command and data
information to the registers of the ICS1893AF.
The ICS1893AF, to transfer status information.
All transfers and sampling are synchronous with the signal on the MDC
pin.
Note: If the ICS1893AF is to be used in an application that uses the
mechanical MII specification, MDIO must have a 1.5 k
±5%
pull-up resistor at the ICS1893AF end and a 2 k
±5% pull-down
resistor at the station management end. (These resistors enable
the station management to determine if the connection is intact.)
RXCLK
34
Output
Receive Clock.
The ICS1893AF sources the RXCLK to the MAC/repeater interface. The
ICS1893AF uses RXCLK to synchronize the signals on the following pins:
RXD[3:0], RXDV, and RXER. The following table contrasts the behavior
on the RXCLK pin when the mode for the ICS1893AF is either 10Base-T
or 100Base-TX.
Note: The signal on the RXCLK pin is conditioned by the RXTRI pin.
Table 9-8.
MAC/Repeater Interface Pins: Media Independent Interface (MII) (Continued)
Pin
Name
Pin
Number
Pin
Type
Pin Description
10Base-T
100Base-TX
The RXCLK frequency is 2.5
MHz.
The RXCLK frequency is 25 MHz.
The ICS1893AF generates its
RXCLK from the MDI data stream
using a digital PLL. When the MDI
data stream terminates, the PLL
continues to operate,
synchronously referenced to the
last packet received.
The ICS1893AF generates its
RXCLK from the MDI data stream
while there is a valid link (that is,
either data or IDLEs). In the
absence of a link, the ICS1893AF
uses the REF_IN clock to
generate the RXCLK.
The ICS1893AF switches
between clock sources during the
period between when its CRS is
asserted and prior to its RXDV
being asserted. While the
ICS1893AF is locking onto the
incoming data stream, a clock
phase change of up to 360
degrees can occur.
While the ICS1893AF is bringing
up a link, a clock phase change of
up to 360 degrees can occur.
The RXCLK aligns once per
packet.
The RXCLK aligns once, when
the link is being established.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ICS1893AFT 功能描述:PHYCEIVER LOW PWR 3.3V 48-SSOP RoHS:否 類別:集成電路 (IC) >> 接口 - 驅(qū)動器，接收器，收發(fā)器 系列:PHYceiver™ 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:收發(fā)器 驅(qū)動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC 包裝:帶卷 (TR)
ICS1893AG 制造商:ICS 制造商全稱:ICS 功能描述:3.3 V 10Base-T/100Base-TX Integrated PHYceiver-TM
ICS1893AGI 制造商:ICS 制造商全稱:ICS 功能描述:3.3 V 10Base-T/100Base-TX Integrated PHYceiver-TM
ICS1893AGILF 制造商:ICS 制造商全稱:ICS 功能描述:3.3 V 10Base-T/100Base-TX Integrated PHYceiver-TM
ICS1893AGLF 制造商:ICS 制造商全稱:ICS 功能描述:3.3 V 10Base-T/100Base-TX Integrated PHYceiver-TM
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