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參數(shù)資料
| 型號： | intel386 SX |
| 廠商： | Intel Corp. |
| 英文描述： | 32-Bit CPU With a 16-Bit External Data Bus And a 24-bit External Address Bus(帶16位內(nèi)部數(shù)據(jù)總線和24位內(nèi)部地址總線32位微處理器) |
| 中文描述： | 32位16位外部數(shù)據(jù)總線和24位外部地址總線CPU（帶16位內(nèi)部數(shù)據(jù)總線和24位內(nèi)部地址總線32位微處理器） |
| 文件頁數(shù)： | 33/102頁 |
| 文件大小： | 1166K |
| 代理商： | INTEL386 SX |
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Intel386
TM
SX MICROPROCESSOR
INITIALIZATION AND TRANSITION TO
PROTECTED MODE
Since the Intel386 SX Microprocessor begins exe-
cuting in Real Mode immediately after RESET it is
necessary to initialize the system tables and regis-
ters with the appropriate values. The GDT and IDT
registers must refer to a valid GDT and IDT. The IDT
should be at least 256 bytes long, and the GDT must
contain descriptors for the initial code and data seg-
ments.
Protected Mode is enabled by loading CR0 with PE
bit set. This can be accomplished by using the
MOV
CR0, R/M
instruction. After enabling Protected
Mode, the next instruction should execute an inter-
segment JMP to load the CS register and flush the
instruction decode queue. The final step is to load all
of the data segment registers with the initial selector
values.
An alternate approach to entering Protected Mode is
to use the built in task-switch to load all of the regis-
ters. In this case the GDT would contain two TSS
descriptors in addition to the code and data descrip-
tors needed for the first task. The first JMP instruc-
tion in Protected Mode would jump to the TSS caus-
ing a task switch and loading all of the registers with
the values stored in the TSS. The Task State Seg-
ment Register should be initialized to point to a valid
TSS descriptor.
4.4 Paging
Paging is another type of memory management use-
ful for virtual memory multi-tasking operating sys-
tems. Unlike segmentation, which modularizes pro-
grams and data into variable length segments, pag-
ing divides programs into multiple uniform size
pages. Pages bear no direct relation to the logical
structure of a program. While segment selectors can
be considered the logical ‘name‘ of a program mod-
ule or data structure, a page most likely corresponds
to only a portion of a module or data structure.
PAGE ORGANIZATION
The Intel386 SX Microprocessor uses two levels of
tables to translate the linear address (from the seg-
mentation unit) into a physical address. There are
three components to the paging mechanism of the
Intel386 SX Microprocessor: the page directory, the
page tables, and the page itself (page frame). All
memory-resident elements of the Intel386 SX Micro-
processor paging mechanism are the same size,
namely 4K bytes. A uniform size for all of the ele-
ments simplifies memory allocation and reallocation
schemes, since there is no problem with memory
fragmentation. Figure 4.10 shows how the paging
mechanism works.
240187–15
Figure 4.10. Paging Mechanism
31
12
11
10
9
8
7
6
5
4
3
2
1
0
System
Software
Defineable
U
D
S
R
D
W
PAGE TABLE ADDRESS 31..12
0
0
D
A
0
0
P
Figure 4.11. Page Directory Entry (Points to Page Table)
33
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| INTEL386 | Intel386 EX Embedded Microprocessor |
| Intel387 dx | DX Math Coprocessor(32位數(shù)學(xué)協(xié)處理器) |
| Intel387 sx | SX Math Coprocessor(32位數(shù)學(xué)協(xié)處理器) |
| INTEL486 GX | Emedded Ultra-Low Power INTEL486 GX Processor(嵌入式超低能量處理器) |
| INTEL486 SX | Emedded Ultra-Low Power INTEL486 SX Processor(嵌入式超低能量處理器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| INTEL387 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel387TM SX MATH COPROCESSOR |
| INTEL387DX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Intel387 DX - MATH COPROCESSOR |
| INTEL387SX | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel387 SX - MATH COPROCESSOR |
| INTEL387TMDX | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel387TM DX MATH COPROCESSOR |
| INTEL740 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:64-Bit Graphics (GUI) Accelerator |
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