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參數(shù)資料
| 型號： | intel386 SX |
| 廠商： | Intel Corp. |
| 英文描述： | 32-Bit CPU With a 16-Bit External Data Bus And a 24-bit External Address Bus(帶16位內(nèi)部數(shù)據(jù)總線和24位內(nèi)部地址總線32位微處理器) |
| 中文描述： | 32位16位外部數(shù)據(jù)總線和24位外部地址總線CPU（帶16位內(nèi)部數(shù)據(jù)總線和24位內(nèi)部地址總線32位微處理器） |
| 文件頁數(shù)： | 36/102頁 |
| 文件大?。?/td> | 1166K |
| 代理商： | INTEL386 SX |
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Intel386
TM
SX MICROPROCESSOR
OPERATING SYSTEM RESPONSIBILITIES
When the operating system enters or exits paging
mode (by setting or resetting bit 31 in the CR0 regis-
ter) a short JMP must be executed to flush the In-
tel386 SX Microprocessor’s prefetch queue. This
ensures that all instructions executed after the ad-
dress mode change will generate correct addresses.
The Intel386 SX Microprocessor takes care of the
page address translation process, relieving the bur-
den from an operating system in a demand-paged
system. The operating system is responsible for set-
ting up the initial page tables and handling any page
faults. The operating system also is required to inval-
idate (i.e. flush) the TLB when any changes are
made to any of the page table entries. The operating
system must reload CR3 to cause the TLB to be
flushed.
Setting up the tables is simply a matter of loading
CR3 with the address of the Page Directory, and
allocating space for the Page Directory and the
Page Tables. The primary responsibility of the oper-
ating system is to implement a swapping policy and
handle all of the page faults.
A final concern of the operating system is to ensure
that the TLB cache matches the information in the
paging tables. In particular, any time the operating
systems sets the P (Present) bit of page table entry
to zero. The TLB must be flushed by reloading CR3.
Operating systems may want to take advantage of
the fact that CR3 is stored as part of a TSS, to give
every task or group of tasks its own set of page
tables.
4.5 Virtual 8086 Environment
The Intel386 SX Microprocessor allows the execu-
tion of 8086 application programs in both Real Mode
and in the Virtual 8086 Mode. The Virtual 8086
Mode allows the execution of 8086 applications,
while still allowing the system designer to take full
advantage of the Intel386 SX CPU’s protection
mechanism.
VIRTUAL 8086 ADDRESSING MECHANISM
One of the major differences between Intel386 SX
CPU Real and Protected modes is how the segment
selectors are interpreted. When the processor is ex-
ecuting in Virtual 8086 Mode, the segment registers
are used in a fashion identical to Real Mode. The
contents of the segment register are shifted left 4
bits and added to the offset to form the segment
base linear address.
The Intel386 SX Microprocessor allows the operat-
ing system to specify which programs use the 8086
address mechanism and which programs use Pro-
tected Mode addressing on a per task basis.
Through the use of paging, the one megabyte ad-
dress space of the Virtual Mode task can be mapped
to anywhere in the 4 gigabyte linear address space
of the Intel386 SX Microprocessor. Like Real Mode,
Virtual Mode addresses that exceed one megabyte
will cause an exception 13. However, these restric-
tions should not prove to be important, because
most tasks running in Virtual 8086 Mode will simply
be existing 8086 application programs.
PAGING IN VIRTUAL MODE
The paging hardware allows the concurrent running
of multiple Virtual Mode tasks, and provides protec-
tion and operating system isolation. Although it is
not strictly necessary to have the paging hardware
enabled to run Virtual Mode tasks, it is needed in
order to run multiple Virtual Mode tasks or to relo-
cate the address space of a Virtual Mode task to
physical address space greater than one megabyte.
The paging hardware allows the 20-bit linear ad-
dress produced by a Virtual Mode program to be
divided into as many as 256 pages. Each one of the
pages can be located anywhere within the maximum
16 megabyte physical address space of the Intel386
SX Microprocessor. In addition, since CR3 (the Page
Directory Base Register) is loaded by a task switch,
each Virtual Mode task can use a different mapping
scheme to map pages to different physical locations.
Finally, the paging hardware allows the sharing of
the 8086 operating system code between multiple
8086 applications.
PROTECTION AND I/O PERMISSION BIT MAP
All Virtual Mode programs execute at privilege level
3. As such, Virtual Mode programs are subject to all
of the protection checks defined in Protected Mode.
This is different than Real Mode, which implicitly is
executing at privilege level 0. Thus, an attempt to
execute a privileged instruction in Virtual Mode will
cause an exception 13 fault.
The following are privileged instructions, which may
be executed only at Privilege Level 0. Attempting to
execute these instructions in Virtual 8086 Mode (or
anytime CPL
t
0) causes an exception 13 fault:
LIDT;
LGDT;
LMSW; MOV CRn,reg;
MOV DRn,REG;
MOV TRn,reg;
MOV reg,DRn;
MOV reg,TRn;
MOV reg,CRn;
CLTS;
HLT;
36
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