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參數(shù)資料
| 型號： | intel386 SX |
| 廠商： | Intel Corp. |
| 英文描述： | 32-Bit CPU With a 16-Bit External Data Bus And a 24-bit External Address Bus(帶16位內(nèi)部數(shù)據(jù)總線和24位內(nèi)部地址總線32位微處理器) |
| 中文描述： | 32位16位外部數(shù)據(jù)總線和24位外部地址總線CPU（帶16位內(nèi)部數(shù)據(jù)總線和24位內(nèi)部地址總線32位微處理器） |
| 文件頁數(shù)： | 59/102頁 |
| 文件大小： | 1166K |
| 代理商： | INTEL386 SX |
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Intel386
TM
SX MICROPROCESSOR
T
h
may be entered from a bus idle state as in Figure
5.16 or after the acknowledgement of the current
physical bus cycle if the LOCK
Y
signal is not assert-
ed, as in Figures 5.17 and 5.18.
T
h
is exited in response to the HOLD input being
negated. The following state will be T
i
as in Figure
5.16 if no bus request is pending. The following bus
state will be T1 if a bus request is internally pending,
as in Figures 5.17 and 5.18. T
h
is exited in response
to RESET being asserted.
If a rising edge occurs on the edge-triggered NMI
input while in T
h
, the event is remembered as a non-
maskable interrupt 2 and is serviced when T
h
is exit-
ed unless the Intel386 SX Microprocessor is reset
before T
h
is exited.
RESET DURING HOLD ACKNOWLEDGE
RESET being asserted takes priority over HOLD be-
ing asserted. If RESET is asserted while HOLD re-
mains asserted, the Intel386 SX Microprocessor
drives its pins to defined states during reset, as in
Table 5.5 Pin State During Reset
, and performs
internal reset activity as usual.
If HOLD remains asserted when RESET is inactive,
the Intel386 SX Microprocessor enters the hold ac-
knowledge state before performing its first bus cy-
cle, provided HOLD is still asserted when the
Intel386 SX Microprocessor would otherwise per-
form its first bus cycle.
240187–31
NOTE:
For maximum design flexibility the Intel386
TM
SX CPU has no internal pullup resistors on its outputs. Your design may
require an external pullup on ADS
Y
and other outputs to keep them negated during float periods.
Figure 5.16. Requesting Hold from Idle Bus
59
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