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參數資料
| 型號： | intel386 SX |
| 廠商： | Intel Corp. |
| 英文描述： | 32-Bit CPU With a 16-Bit External Data Bus And a 24-bit External Address Bus(帶16位內部數據總線和24位內部地址總線32位微處理器) |
| 中文描述： | 32位16位外部數據總線和24位外部地址總線CPU（帶16位內部數據總線和24位內部地址總線32位微處理器） |
| 文件頁數： | 60/102頁 |
| 文件大小： | 1166K |
| 代理商： | INTEL386 SX |
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Intel386
TM
SX MICROPROCESSOR
FLOAT
Activating the FLT
Y
input floats all Intel386 SX bidi-
rectional and output signals, including HLDA. Assert-
ing FLT
Y
isolates the Intel386 SX from the sur-
rounding circuitry.
As the Intel386 SX is packaged in a surface mount
PQFP, it cannot be removed from the motherboard
when In-Circuit Emulation (ICE) is needed. The
FLT
Y
input allows the Intel386 SX to be electrically
isolated from the surrounding circuitry. This allows
connection of an emulator to the Intel386 SX PQFP
without removing it from the PCB. This method of
emulation is referred to as ON-Circuit Emulation
(ONCE).
ENTERING AND EXITING FLOAT
FLT
Y
is an asynchronous, active-low input. It is rec-
ognized on the rising edge of CLK2. When recog-
nized, it aborts the current bus cycle and floats the
outputs of the Intel386 SX (Figure 5.20). FLT
Y
must
be held low for a minimum of 16 CLK2 cycles. Reset
should be asserted and held asserted until after
FLT
Y
is deasserted. This will ensure that the
Intel386 SX will exit float in a valid state.
Asserting the FLT
Y
input unconditionally aborts the
current bus cycle and forces the Intel386 SX into the
FLOAT mode. Since activating FLT
Y
unconditional-
ly forces the Intel386 SX into FLOAT mode, the
Intel386 SX is not guaranteed to enter FLOAT in a
valid state. After deactivating FLT
Y
, the Intel386 SX
is not guaranteed to exit FLOAT mode in a valid
state. This is not a problem as the FLT
Y
pin is
meant to be used only during ONCE. After exiting
FLOAT, the Intel386 SX must be reset to return it to
a valid state. Reset should be asserted before FLT
Y
is deasserted. This will ensure that the Intel386 SX
will exit float in a valid state.
FLT
Y
has an internal pull-up resistor, and if it is not
used it should be unconnected.
BUS ACTIVITY DURING AND FOLLOWING
RESET
RESET is the highest priority input signal, capable of
interrupting any processor activity when it is assert-
ed. A bus cycle in progress can be aborted at any
stage, or idle states or bus hold acknowledge states
discontinued so that the reset state is established.
240187–32
NOTE:
HOLD is a synchronous input and can be asserted at any CLK2 edge, provided setup and hold (t
23
and t
24
) require-
ments are met. This waveform is useful for determining Hold Acknowledge latency.
Figure 5.17. Requesting Hold from Active Bus (NA
Y
inactive)
60
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| INTEL486 GX | Emedded Ultra-Low Power INTEL486 GX Processor(嵌入式超低能量處理器) |
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相關代理商/技術參數 |
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|---|---|
| INTEL387 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel387TM SX MATH COPROCESSOR |
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| INTEL387TMDX | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel387TM DX MATH COPROCESSOR |
| INTEL740 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:64-Bit Graphics (GUI) Accelerator |
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