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參數(shù)資料
| 型號： | intel386 SX |
| 廠商： | Intel Corp. |
| 英文描述： | 32-Bit CPU With a 16-Bit External Data Bus And a 24-bit External Address Bus(帶16位內部數(shù)據(jù)總線和24位內部地址總線32位微處理器) |
| 中文描述： | 32位16位外部數(shù)據(jù)總線和24位外部地址總線CPU（帶16位內部數(shù)據(jù)總線和24位內部地址總線32位微處理器） |
| 文件頁數(shù)： | 4/102頁 |
| 文件大?。?/td> | 1166K |
| 代理商： | INTEL386 SX |
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Intel386
TM
SX MICROPROCESSOR
1.0 PIN DESCRIPTION
(Continued)
The following are the Intel386
TM
SX Microprocessor pin descriptions. The following definitions are used in the
pin descriptions:
Y
I
O
I/O
-
The named signal is active LOW.
Input signal.
Output signal.
Input and Output signal.
No electrical connection.
Symbol
Type
Pin
Name and Function
CLK2
I
15
CLK2
provides the fundamental timing for the Intel386 SX
Microprocessor. For additional information see
Clock.
RESET
I
33
RESET
suspends any operation in progress and places the
Intel386 SX Microprocessor in a known reset state. See
Interrupt Signals
for additional information.
D
15
–D
0
I/O
81-83,86-90,
92-96,99-100,1
Data Bus
inputs data during memory, I/O and interrupt
acknowledge read cycles and outputs data during memory and
I/O write cycles. See
Data Bus
for additional information.
A
23
–A
1
O
80-79,76-72,70,
66-64,62-58,
56-51,18
Address Bus
outputs physical memory or port I/O addresses.
See
Address Bus
for additional information.
W/R
Y
O
25
Write/Read
is a bus cycle definition pin that distinguishes write
cycles from read cycles. See
Bus Cycle Definition Signals
for
additional information.
D/C
Y
O
24
Data/Control
is a bus cycle definition pin that distinguishes data
cycles, either memory or I/O, from control cycles which are:
interrupt acknowledge, halt, and code fetch. See
Bus Cycle
Definition Signals
for additional information.
M/IO
Y
O
23
Memory/IO
is a bus cycle definition pin that distinguishes
memory cycles from input/output cycles. See
Bus Cycle
Definition Signals
for additional information.
LOCK
Y
O
26
Bus Lock
is a bus cycle definition pin that indicates that other
system bus masters are not to gain control of the system bus
while it is active. See
Bus Cycle Definition Signals
for
additional information.
ADS
Y
O
16
Address Status
indicates that a valid bus cycle definition and
address (W/R
Y
, D/C
Y
, M/IO
Y
, BHE
Y
, BLE
Y
and A
23
–A
1
are
being driven at the Intel386 SX Microprocessor pins. See
Bus
Control Signals
for additional information.
NA
Y
I
6
Next Address
is used to request address pipelining. See
Bus
Control Signals
for additional information.
READY
Y
I
7
Bus Ready
terminates the bus cycle. See
Bus Control Signals
for additional information.
BHE
Y
, BLE
Y
O
19,17
Byte Enables
indicate which data bytes of the data bus take part
in a bus cycle. See
Address Bus
for additional information.
4
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相關代理商/技術參數(shù) |
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