參數(shù)資料
型號(hào)： intel386 SX
廠商： Intel Corp.
英文描述： 32-Bit CPU With a 16-Bit External Data Bus And a 24-bit External Address Bus(帶16位內(nèi)部數(shù)據(jù)總線和24位內(nèi)部地址總線32位微處理器)
中文描述： 32位16位外部數(shù)據(jù)總線和24位外部地址總線CPU（帶16位內(nèi)部數(shù)據(jù)總線和24位內(nèi)部地址總線32位微處理器）
文件頁(yè)數(shù)： 42/102頁(yè)
文件大?。?/td> 1166K
代理商： INTEL386 SX
Intel386
TM
SX MICROPROCESSOR
BUS CONTROL SIGNALS
(ADS
Y
, READY
Y
, NA
Y
)
The following signals allow the processor to indicate
when a bus cycle has begun, and allow other system
hardware to control address pipelining and bus cycle
termination.
Address Status (ADS
Y
)
This three-state output indicates that a valid bus cy-
cle definition and address (W/R
Y
, D/C
Y
, M/IO
Y
,
BHE
Y
, BLE
Y
and A
23
–A
1
) are being driven at the
Intel386 SX Microprocessor pins. ADS
Y
is an active
LOW output. Once ADS
Y
is driven active, valid ad-
dress, byte enables, and definition signals will not
change. In addition, ADS
Y
will remain active until its
associated bus cycle begins (when READY
Y
is re-
turned for the previous bus cycle when running pipe-
lined bus cycles). When address pipelining is uti-
lized, maximum throughput is achieved by initiating
bus cycles when ADS
Y
and READY
Y
are active in
the same clock cycle. ADS
Y
will float during bus
hold acknowledge. See sections
Non-Pipelined Ad-
dress
and
Pipelined Address
for additional infor-
mation on how ADS
Y
is asserted for different bus
states.
Transfer Acknowledge (READY
Y
)
This input indicates the current bus cycle is com-
plete, and the active bytes indicated by BHE
Y
and
BLE
Y
are accepted or provided. When READY
Y
is
sampled active during a read cycle or interrupt ac-
knowledge cycle, the Intel386 SX Microprocessor
latches the input data and terminates the cycle.
When READY
Y
is sampled active during a write cy-
cle, the processor terminates the bus cycle.
READY
Y
is ignored on the first bus state of all bus
cycles, and sampled each bus state thereafter until
asserted. READY
Y
must eventually be asserted to
acknowledge every bus cycle, including Halt Indica-
tion and Shutdown Indication bus cycles. When be-
ing sampled, READY
Y
must always meet setup and
hold times t
19
and t
20
for correct operation.
Next Address Request (NA
Y
)
This is used to request address pipelining. This input
indicates the system is prepared to accept new val-
ues of BHE
Y
, BLE
Y
, A
23
–A
1
, W/R
Y
, D/C
Y
and
M/IO
Y
from the Intel386 SX Microprocessor even if
the end of the current cycle is not being acknowl-
edged on READY
Y
. If this input is active when sam-
pled, the next address is driven onto the bus, provid-
ed the next bus request is already pending internally.
NA
Y
is ignored in CLK cycles in which ADS
Y
or
READY
Y
is activated. This signal is active LOW and
must satisfy setup and hold times t
15
and t
16
for
correct operation. See
Pipelined Address
and
Read and Write Cycles
for additional information.
BUS ARBITRATION SIGNALS (HOLD, HLDA)
This section describes the mechanism by which the
processor relinquishes control of its local buses
when requested by another bus master device. See
Entering and Exiting Hold Acknowledge
for addi-
tional information.
Bus Hold Request (HOLD)
This input indicates some device other than the
Intel386 SX Microprocessor requires bus master-
ship. When control is granted, the Intel386 SX Mi-
croprocessor floats A
23
–A
1
, BHE
Y
, BLE
Y
, D
15
–
D
0
, LOCK
Y
, M/IO
Y
, D/C
Y
, W/R
Y
and ADS
Y
, and
then activates HLDA, thus entering the bus hold ac-
knowledge state. The local bus will remain granted
to the requesting master until HOLD becomes inac-
tive. When HOLD becomes inactive, the Intel386 SX
Microprocessor will deactivate HLDA and drive the
local bus (at the same time), thus terminating the
hold acknowledge condition.
HOLD must remain asserted as long as any other
device is a local bus master. External pull-up resis-
tors may be required when in the hold acknowledge
state since none of the Intel386 SX Microprocessor
floated outputs have internal pull-up resistors. See
Resistor Recommendations
for additional informa-
tion. HOLD is not recognized while RESET is active.
If RESET is asserted while HOLD is asserted, RE-
SET has priority and places the bus into an idle
state, rather than the hold acknowledge (high-im-
pedance) state.
HOLD is a level-sensitive, active HIGH, synchronous
input. HOLD signals must always meet setup and
hold times t
23
and t
24
for correct operation.
Bus Hold Acknowledge (HLDA)
When active (HIGH), this output indicates the
Intel386 SX Microprocessor has relinquished control
of its local bus in response to an asserted HOLD
signal, and is in the bus Hold Acknowledge state.
The Bus Hold Acknowledge state offers near-com-
plete signal isolation. In the Hold Acknowledge
state, HLDA is the only signal being driven by the
Intel386 SX Microprocessor. The other output sig-
nals or bidirectional signals (D
15
–D
0
, BHE
Y
, BLE
Y
,
A
23
–A
1
, W/R
Y
, D/C
Y
, M/IO
Y
, LOCK
Y
ADS
Y
) are in a high-impedance state so the re-
and
42
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