參數(shù)資料
型號： intel386 SX
廠商： Intel Corp.
英文描述： 32-Bit CPU With a 16-Bit External Data Bus And a 24-bit External Address Bus(帶16位內(nèi)部數(shù)據(jù)總線和24位內(nèi)部地址總線32位微處理器)
中文描述： 32位16位外部數(shù)據(jù)總線和24位外部地址總線CPU（帶16位內(nèi)部數(shù)據(jù)總線和24位內(nèi)部地址總線32位微處理器）
文件頁數(shù)： 92/102頁
文件大小： 1166K
代理商： INTEL386 SX
Intel386
TM
SX MICROPROCESSOR
Table 9-1. Instruction Set Clock Count Summary
(Continued)
CLOCK COUNT
NOTES
Real
Address
Mode or
Virtual
8086
Mode
Real
Address
Mode or
Virtual
8086
Mode
INSTRUCTION
FORMAT
Protected
Virtual
Address
Mode
Protected
Virtual
Address
Mode
INTERRUPT INSTRUCTIONS
(Continued)
BOUND:
Via Interrupt or Trap Gate
to Same Privilege Level
Via Interrupt or Trap Gate
to Different Privilege Level
From 286 Task to 286 TSS via Task Gate
From 286 Task to Intel386
TM
SX CPU TSS via Task Gate
From 268 Task to virt 8086 Mode via Task Gate
From Intel386 SX CPU Task to 286 TSS via Task Gate
From Intel386 SX CPU Task to Intel386 SX CPU TSS via Task Gate
From Intel386 SX CPU Task to virt 8086 Mode via Task Gate
From virt 8086 Mode to 286 TSS via Task Gate
From virt 8086 Mode to Intel386 SX CPU TSS via Task Gate
From virt 8086 md to priv level 0 via Trap Gate or Interrupt Gate
71
g, j, k, r
111
358
388
335
368
398
347
368
398
223
g, j, k, r
g, j, k, r
g, j, k, r
g, j, k, r
g, j, k, r
g, j, k, r
g, j, k, r,
g, j, k, r
g, j, k, r
INTERRUPT RETURN
IRET
e
Interrupt Return
1 1 0 0 1 1 1 1
24
g, h, j, k, r
Protected Mode Only (IRET)
To the Same Privilege Level (within task)
To Different Privilege Level (within task)
From 286 Task to 286 TSS
From 286 Task to Intel386 SX CPU TSS
From 286 Task to Virtual 8086 Task
From 286 Task to Virtual 8086 Mode (within task)
From Intel386 SX CPU Task to 286 TSS
From Intel386 SX CPU Task to Intel386 SX CPU TSS
From Intel386 SX CPU Task to Virtual 8086 Task
From Intel386 SX CPU Task to Virtual 8086 Mode (within task)
42
86
285
318
267
113
324
328
377
113
g, h, j, k, r
g, h, j, k, r
h, j, k, r
h, j, k, r
h, j, k, r
h, j, k, r
h, j, k, r
h, j, k, r
PROCESSOR CONTROL
HLT
e
HALT
1 1 1 1 0 1 0 0
5
5
l
MOV
e
Move to and From Control/Debug/Test Registers
CR0/CR2/CR3 from register
0 0 0 0 1 1 1 1
0 0 1 0 0 0 1 0
1 1 eee reg
10/4/5
10/4/5
l
Register From CR0–3
0 0 0 0 1 1 1 1
0 0 1 0 0 0 0 0
1 1 eee reg
6
6
l
DR0–3 From Register
0 0 0 0 1 1 1 1
0 0 1 0 0 0 1 1
1 1 eee reg
22
22
l
DR6–7 From Register
0 0 0 0 1 1 1 1
0 0 1 0 0 0 1 1
1 1 eee reg
16
16
l
Register from DR6–7
0 0 0 0 1 1 1 1
0 0 1 0 0 0 0 1
1 1 eee reg
14
14
l
Register from DR0–3
0 0 0 0 1 1 1 1
0 0 1 0 0 0 0 1
1 1 eee reg
22
22
l
TR6–7 from Register
0 0 0 0 1 1 1 1
0 0 1 0 0 1 1 0
1 1 eee reg
12
12
l
Register from TR6–7
0 0 0 0 1 1 1 1
0 0 1 0 0 1 0 0
1 1 eee reg
12
12
l
NOP
e
No Operation
1 0 0 1 0 0 0 0
3
3
WAIT
e
Wait until BUSY
Y
pin is negated
1 0 0 1 1 0 1 1
6
6
92
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